R5F10366ASP datasheet(87/114 Pages) RENESAS

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RL78/G12

3. ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = –40 to +105°C)

R01DS0193EJ0250 Rev.2.50

Jan 17, 2025

Page 87 of 109

(6) Communication at different potential (1.8 V, 2.5 V, 3 V) (simplified SPI (CSI) mode) (master mode, SCKp...

internal clock output) (3/3)

(TA = –40 to +105°C, 2.4 V ≤ VDD ≤ 5.5 V, VSS = 0 V)

Parameter

Symbol

Conditions

HS (high-speed main) Mode

Unit

MIN.

MAX.

SIp setup time (to SCKp

↓)

Note

tSIK1

4.0 V

≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V,

Cb = 30 pF, Rb = 1.4 k

2.7 V

≤ VDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V,

Cb = 30 pF, Rb = 2.7 k

2.4 V

≤ VDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V,

Cb = 30 pF, Rb = 5.5 k

220

SIp hold time

(from SCKp

↓) Note

tKSI1

4.0 V

≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V,

Cb = 30 pF, Rb = 1.4 k

2.7 V

≤ VDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V,

Cb = 30 pF, Rb = 2.7 k

2.4 V

≤ VDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V,

Cb = 30 pF, Rb = 5.5 k

Delay time from SCKp

↑ to

SOp output Note

tKSO1

4.0 V

≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V,

Cb = 30 pF, Rb = 1.4 k

2.7 V

≤ VDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V,

Cb = 30 pF, Rb = 2.7 k

2.4 V

≤ VDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V,

Cb = 30 pF, Rb = 5.5 k

Note When DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.

Cautions 1.

Select the TTL input buffer for the SIp pin and the N-ch open drain output (VDD tolerance) mode

for the SOp pin and SCKp pin by using port input mode register 1 (PIM1) and port output mode

CSI01 and CSI11 cannot communicate at different potential.

Remarks 1.

Rb [

Ω]: Communication line (SCKp, SOp) pull-up resistance, Cb [F]: Communication line (SCKp, SOp)

load capacitance, Vb [V]: Communication line voltage

p: CSI number (p = 00, 20), m: Unit number (m = 0, 1), n: Channel number (n = 0)

Simplified SPI (CSI) mode connection diagram (during communication at different potential)

SCKp

SOp

SCK

User's device

SIp

RL78

microcontroller

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