R5F10366ASP datasheet(28/114 Pages) RENESAS

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RL78/G12

2. ELECTRICAL SPECIFICATIONS (TA = –40 to +85°C)

R01DS0193EJ0250 Rev.2.50

Jan 17, 2025

Page 28 of 109

2.4 AC Characteristics

(TA = –40 to +85°C, 1.8 V ≤ VDD ≤ 5.5 V, VSS = 0 V)

Items

Symbol

Conditions

MIN.

TYP.

MAX.

Unit

Instruction cycle (minimum

instruction execution time)

TCY

Main system

clock (fMAIN)

operation

HS (High-

speed main)

mode

2.7 V

≤ VDD ≤ 5.5 V

0.04167

µs

2.4 V

≤ VDD < 2.7 V

0.0625

µs

LS (Low-

speed main)

mode

1.8 V

≤ VDD ≤ 5.5 V

0.125

µs

During self

programming

HS (High-

speed main)

mode

2.7 V

≤ VDD ≤ 5.5 V

0.04167

µs

2.4 V

≤ VDD < 2.7 V

0.0625

µs

LS (Low-

speed main)

mode

1.8 V

≤ VDD ≤ 5.5 V

0.125

µs

External main system clock

frequency

fEX

2.7 V

≤ VDD ≤ 5.5 V

1.0

20.0

MHz

2.4 V

≤ VDD < 2.7 V

1.0

16.0

MHz

1.8 V

≤ VDD < 2.4 V

1.0

8.0

MHz

External main system clock

input high-level width, low-

level width

tEXH, tEXL

2.7 V

≤ VDD ≤ 5.5 V

2.4 V

≤ VDD < 2.7 V

1.8 V

≤ VDD < 2.4 V

TI00 to TI07 input high-level

width, low-level width

tTIH, tTIL

1/fMCK +

TO00 to TO07 output

frequency

fTO

4.0 V

≤ VDD ≤ 5.5 V

MHz

2.7 V

≤ VDD < 4.0 V

MHz

1.8 V

≤ VDD < 2.7 V

MHz

PCLBUZ0, or PCLBUZ1

output frequency

fPCL

4.0 V

≤ VDD ≤ 5.5 V

MHz

2.7 V

≤ VDD < 4.0 V

MHz

1.8 V

≤ VDD < 2.7 V

MHz

INTP0 to INTP5 input high-

level width, low-level width

tINTH, tINTL

µs

KR0 to KR9 input available

width

tKR

250

RESET low-level width

tRSL

µs

Remark

fMCK: Timer array unit operation clock frequency

(Operation clock to be set by the timer clock select register 0 (TPS0) and the CKS0n bit of timer mode

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