M32CSLASH8B datasheet(144/406 Pages) RENESAS

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Under development

M32C/8B Group

13. DMAC

Preliminary specification

Specifications in this manual are tentative and subject to change.

REJ09B0450-0050 Rev.0.50 Oct 31, 2008

Page 127 of 385

Figure 13.6

DMD1 Register

DMA Mode Register 1(1)

Symbol

DMD1

Address

(CPU internal register)

Bit Symbol

MD20

After Reset

00h

NOTE:

1. Use the LDC instruction to set the DMD1 register.

MD21

BW2

RW2

MD30

MD31

BW3

RW3

b7 b6 b5 b4

Bit Name

Channel 2

transfer mode select bits

Channel 3

transfer unit select bit

Channel 3

transfer direction select bit

Channel 2

transfer unit select bit

Channel 2

transfer direction select bit

Channel 3

transfer mode select bits

b1 b0

0 0: DMA disabled

0 1: Single transfer

1 0: Do not set to this value

1 1: Repeat transfer

0: 8 bits

1: 16 bits

b5 b4

0 0: DMA disabled

0 1: Single transfer

1 0: Do not set to this value

1 1: Repeat transfer

0: 8 bits

1: 16 bits

0: Fixed address to incremented address

1: Incremented address to fixed address

0: Fixed address to incremented address

1: Incremented address to fixed address

Function

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