M32CSLASH8B datasheet(148/406 Pages) RENESAS

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M32C/8B Group

13. DMAC

Preliminary specification

Specifications in this manual are tentative and subject to change.

REJ09B0450-0050 Rev.0.50 Oct 31, 2008

Page 131 of 385

13.2

DMA Transfer Time

The DMA transfer time can be calculated as follows. (in terms of bus clock)

Table 13.3 lists the number of the source read cycle and destination write cycle. Table 13.4 lists coefficient j, k (the

number of bus clock).

Transfer time = source read bus cycle × j + destination write bus cycle × k

Table 13.3

Source Read Cycle and Destination Write Cycle

i=0 to 3, p=0 and 1

Table 13.4

Coefficient j, k

13.3

Channel Priority and DMA Transfer Timing

When multiple DMA requests are generated in the same sampling period (between a falling edge of the BCLK and

the next falling edge), the corresponding DRQ bits in the DMiSL register (i = 0 to 3) are set to 1 (requested)

simultaneously. Channel priority in this case is: DMA0 > DMA1 > DMA2 > DMA3. Leave the following period

between each DMA transfer request generation on the same channel.

DMA request interval

≥ (number of channels set for DMA transfer - 1) × 5 BCLK cycles

Described in the following is the operation when DMA0 and DMA1 requests are generated in the same sampling

period. Figure 13.9 shows an example of DMA transfers triggered by the INT interrupts.

In Figure 13.9, DMA0 and DMA1 requests are generated simultaneously. A DMA0 request having higher priority

is acknowledged first to start a transfer. After one DMA0 transfer is completed, the DMAC returns ownership of

the bus to the CPU. When the CPU has completed one bus access, a DMA1 transfer starts. After one DMA1

transfer is completed, bus ownership is again returned to the CPU.

DMA requests cannot be counted up since each channel has one DRQ bit. Even if multiple DMA1 requests are

generated before receiving bus ownership as shown in Figure 13.9, the DRQ bit is set to 0 as soon as bus ownership

is acquired. Bus ownership is returned to the CPU after one transfer is completed.

Transfer Unit

Bus Width

Access

Address

Accessing Internal Space

Accessing External Space

Read Cycle

Write Cycle

Read Cycle

Write Cycle

8-bit transfer

(BWi bit in the DMDp

16 bits

Even

Odd

8 bits

Even

−−

Odd

−−

16-bit transfer

(BWi bit = 1)

16 bits

Even

Odd

8 bits

Even

−−

Odd

−−

Internal Space

External Space

Internal ROM or

internal RAM

Internal ROM or

internal RAM

SFR area

j and k BCLK cycles shown in Table 8.6 (j, k = 2 to 9).

Add one cycle to j or k cycles when inserting a recovery

cycle

with no wait state

j=1

k=1

with wait state

j=2

k=2

j=2

k=2

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