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Debug and Logic Analyzer Mode

Intel® 6400/6402 Advanced Memory Buffer Datasheet

5.1.8.5

Qualification

The AMB in LAI mode sends a qualification signal, QUAL, on a DDR pin along with each

frame. A qualified frame contains data likely to be of interest to the user of the logic

analyzer. Conversely, an unqualified frame has been chosen to be filtered out because it

only contains idle NOP frames or has otherwise been “flagged” as not occurring

between pre-selected events. The logic analyzer can capture data when QUAL is

asserted, and ignore data when QUAL is deasserted.

Once a qualified frame is seen, the QUAL signal is asserted, and it remains asserted for

an additional programmable number of cycles, using a timer ranging from 0 to 63. This

timer is restarted if it is already running when a new qualified frame is seen.

The error injection timer will be used to push out the triggering of the QUAL_STOP

signal by N timer count of clock cycles (where N is user programmed for delay range of

0 to 63), thus increasing the length of the QUAL_FLAG interval. One QUAL_START

event will enable the assertion of QUAL_FLAG and another QUAL_STOP event will

disable assertion of QUAL_FLAG.

A frame of all NOPs is not a qualified frame. A sync frame is not a qualified frame if the

FILTER_SYNC configuration register bit is set; otherwise it is considered qualified.

Note:

The ability to determine which frames are qualified may be lost following an unmasked

CRC or Few Edges error. This is the result of the architected behavior that future

commands following the error will ignored. As a side effect, QUAL may stay high once

these errors are detected.

If the QUAL_MODE configuration register bit is set, frames must additionally occur

between QUAL_START and QUAL_STOP events to be qualified. A frame that triggers

QUAL_START may also cause the QUAL signal to assert, and a frame that triggers

QUAL_STOP will not be considered qualified. The QUAL_START and QUAL_STOP events

are programmable and are selected from the 32 local events.

Figure 5-8 is a block diagram of the qualification signal control logic.

Figure 5-8. LAI Qualification Signal Block Diagram

QUALSTOPDELAY[5:0]

Command <> NOP

Command A

Command <> SYNC

Format = cmd+wdata

Command B

Command C

Command <> NOP

AND

input

load

dec

FILTER_SYNC

set

clr

local events

QU AL_FLAG

AND

QUAL_ST ART[4:0]

QUAL_STOP[4:0]

QUAL_PERIOD[5:0]

QUAL_MO DE

QUAL

Timer

0… 63

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