6402 datasheet(61/250 Pages) INTEL

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Intel® 6400/6402 Advanced Memory Buffer Datasheet

Debug and Logic Analyzer Mode

5.1.8.2.1

Additional Qualification on Match/Mask

Full frame and A-slot matching is enabled part way through TS0, once FBD inputs have

been aligned with the core clocking phases. Though generally, will not be used until link

has completed initialization.

Slot B and Slot C pattern matching is further qualified so that true commands can be

differentiated from data when not doing full frame matching.

For each mask and match pair 0, 1 or 2

• If Mask[39] = 1, then match and mask against any received data in Slot B and Slot

• If Mask[39] = 0 AND Match[39] = 0 then only match on commands.

— Ignore a match with contents of Slot B if

Frame type is not Command or

Frame type is command and A-command is Sync or Soft Reset

— Ignore a match with contents of Slot C if

Frame type is not Command or

Frame type is command and A-command is Sync or Soft Reset or

B-command is Write Configuration Register

Figure 5-4. LAI Match and Mask Logic

A matches 2

C matches 2

B matches 2

B matches 1

C matches 1

A matches 1

A matches 0

C matches 0

B matches 0

13:1 mux

M&M CmdA

MM_12

MM_10

MM_11

Match

Events

MM_8

MM_5

MM_2

MM_1

MM_6

MM_7

MM_4

MM_0

MM_9

MM_3

MMEVENT[0

MMEVENT[1

MMEVENT[2]

Cmd

Qual

Logic

Cmd

Qual

Logic

Cmd

Qual

Logic

OR – match

0 in any pos

Mask &

match A

Cmd slot

Mask &

match B

Cmd slot

Mask &

match C

Cmd slot

Combining

Results

& Reg.

Combining

Results

& Reg.

Combining

Results

& Reg.

M&M CmdB

M&M CmdC

M&M CmdA

M&M CmdB

M&M CmdC

OR -match 1

in any pos

OR – match

2 in any pos

AND

(full frame)

Match & Mask

Registers for

Cmnd #0

Match & Mask

Registers for

Cmnd #1

Match & Mask

Registers for

Cmnd #2

Early Southbound

Pipeline stage

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