6402 datasheet(8/250 Pages) INTEL

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Intel® 6400/6402 Advanced Memory Buffer Datasheet

10-2 Block Diagram for the AMB in transparent mode .................................................. 100

10-1 Transparent Mode Timing ................................................................................. 103

10-2 Transparent Mode Write Timing ......................................................................... 104

10-3 Transparent Mode Read Timing.......................................................................... 105

10-4 BL=8 Read Timing ........................................................................................... 105

11-1 Range and Full Address Spaces.......................................................................... 117

11-2 Fast Y Address Sequencing ............................................................................... 119

11-3 Fast X Address Sequencing ............................................................................... 120

11-4 Fast XY Address Sequencing Examples ............................................................... 121

11-5 MemBIST Circular Shift and LFSR Data Block Diagram .......................................... 124

11-6 MemBIST Block Diagram .................................................................................. 138

11-7 MBFSM Diagram .............................................................................................. 139

11-8 CS State Machine ............................................................................................ 141

12-1 Pinout Configuration......................................................................................... 143

12-2 Bottom View ................................................................................................... 152

12-3 Top View ........................................................................................................ 153

12-4 Package Stackup ............................................................................................. 154

Tables

3-1

DQS Association with DQ/CB Pins in x8 and x4 Mode ..............................................27

4-1

Absolute Maximum Ratings Over Operating Free-Air Temperature Range

(See Note 1) .....................................................................................................37

4-2

AMB Operating DC Electrical Parameters ...............................................................37

4-3

Power Values for x8 DIMMS ................................................................................38

4-4

Power Values for x4 DIMMs .................................................................................41

4-5

AMB FB-DIMM Timing/Electrical ...........................................................................44

4-6

AMB FB-DIMM Latency .......................................................................................44

4-7

Recommended Operating Conditions for DRAM Interface .........................................45

4-8

Advance Memory Buffer Component DDR2 Electrical Timing Specifications.................50

4-9

Advance Memory Buffer DDR2 Package Lengths.....................................................51

4-10 Recommended Operating Conditions for SMBUS Interface .......................................51

4-11 Recommended Operating Conditions for RESET and BFUNC Pins...............................51

5-1

DDR Pins Shared With LAI Functionality ................................................................56

5-2

List of Pins Required to Enable Debug With LAI Functionality ...................................56

5-3

LAI Mode Added Signals .....................................................................................56

5-4

List of Shared DDR/LAI Pins ................................................................................57

5-5

Typical FBD Southbound Command Frame ............................................................59

5-6

LAI Local Events ................................................................................................62

5-7

LAI Event Selection ............................................................................................63

6-1

Link Errors in Initialization ..................................................................................71

6-2

Link Errors in Normal Operation ...........................................................................72

6-3

DDR Errors .......................................................................................................73

6-4

Host Protocol Errors ...........................................................................................73

6-5

Other Errors......................................................................................................74

7-1

SMBus Command Encoding .................................................................................78

7-2

SMBus Protocol Addressing Fields ........................................................................78

7-3

Status Field Encoding for SMBus Reads.................................................................79

8-1

PLL Clocks ........................................................................................................85

8-2

AMB Clock Ratios ...............................................................................................86

8-3

Clock Pins.........................................................................................................86

10-1 Additional Signals in Transparent Mode............................................................... 101

6402 Datasheet(PDF) 8 Page - Intel Corporation

6402 Datasheet(HTML) 8 Page - Intel Corporation

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