6402 datasheet(57/250 Pages) INTEL

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Intel® 6400/6402 Advanced Memory Buffer Datasheet

Debug and Logic Analyzer Mode

5.1.5

LAI to DDR Pin Mapping

Table 5-4 contains the LAI-to-DDR pin mapping.

CLK

Out

Logic analyzer reference clock (differential). This provides a LA

compatible timing reference clock for capture of all signals to the

LA, with fine capture phase adjust using the native LA clock edge

offset capabilities.

QUAL

Out

Store qualifier:

1 = store

0 = do not store

FRAME

Out

Drives 1 when LAI pins are valid level. Should be connected to

pull down on LAI board to detect when LAI pins are tri-stated

and LA should ignore data.

EV[3:0]

I/O

Inter-AMB event bus for cross-triggering (wired-OR, high active,

slow).This four bit event bus allows multiple AMB (and similar)

LAIs to be programmed to inter-communicate locally detected

matching and/or filtering opportunities events (cross-triggering

and cross-qualification).

Table 5-3.

LAI Mode Added Signals (Sheet 2 of 2)

Signal Type

Direction

Definition

Table 5-4.

List of Shared DDR/LAI Pins (Sheet 1 of 2)

DDR Pin

Count

Speed Mbit/sec

LAI Mode

Comment

DQ[55:52], DQS[15],

DQS[15]

533/667

sbframe_data0[5:0],

[11:6]

5:0 captured on rising

edge of CLK,

11:6 captured on falling

edge of CLK

DQ[59:56], DQS[7],

DQS[7]

533/667

sbframe_data1[5:0],

[11:6]

DQ[51:48], DQS[6],

DQS[6]

533/667

sbframe_data2[5:0],

[11:6]

DQ[39:36], DQS[13],

DQS[13]

533/667

sbframe_data3[5:0],

[11:6]

DQ[47:44], DQS[14],

DQS[14]

533/667

sbframe_data4[5:0],

[11:6]

DQ[35:32], DQS[4],

DQS[4]

533/667

sbframe_data5[5:0],

[11:6]

DQ[43:40], DQS[5],

DQS[5]

533/667

sbframe_data6[5:0],

[11:6]

RASB, A[10:9)B,

DYBA[2:0]B

533/667

sbframe_data7[5:0],

[11:6]

A[6:2]B, A[0]B

533/667

sbframe_data8[5:0],

[11:6]

A[15:11],B A[8]B

533/667

sbframe_data9[5:0],

[11:6]

CKE[1:0]B, CS[1:0]B,

ODTB,

267/333

trigger[10:6]

Will only change at 1/2

freq

BA[2]A

533/667

frame

1 if transferring first half

of frame, 0 if second half

CASB, WEB, A[7]B,

A[1]B

100 MHz

evbus[3:0]

Inner DY bumpout rows

CASA

267/333

mode

RASA

267/333

qual

CKE[1:0]A, CS[1:0]A,

ODTA, WEA

267/333

trigger[5:0]

Will only change at 1/2

freq

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