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Intel® 6400/6402 Advanced Memory Buffer Datasheet

Debug and Logic Analyzer Mode

5.1.2

LAI Mode Clocking

To eliminate frequency drifts, the AMB on each DIMM and the chipset in an FBD channel

will be provided with a reference clock that is from a clock source common to the FBD

channel. A clock buffer will be placed on the LAI card to take the reference clock input

and provide the required two reference clocks for the LAI AMB and the attached DIMM

AMB.

5.1.3

LAI Mode Pins

The DDR pins designed in the AMB can be enabled to carry signals for the logic analyzer

debug and validation of the FBD channel. The LAI mode is selected by strapping the

following input pins on a AMB which has the LAI capability bit enabled.

SA[:0] = DIMM ID = 4b’11XX

The list below highlights the pins in the AMB that are dedicated for DDR, all of which

are not required to operate at speed equal to the DDR data rate.

Address/Command pins are specially designed in the AMB to be able to drive double

data rate to support the LAI functionality.

Figure 5-2. AMB LAI Mode Connectivity

Reference clock

Southbound In

Northbound Out

Southbound Out

Northbound In

1 x2

10 x2

14 x2

S[59:00]

CLK[p,n]

Southbound

and northbound

signals to

logic analyzer

To next DIMM

to the South

To MCH or

next DIMM

to the North

AMB in LAI Mode

10 x2

14 x2

1 x2

SMB

TRIG[10:0]

Shared signals to

logic analyzer

QUAL

MODE

FRAME

N[83:00]

EV[3:0]

Shared signals to

other trace Bds

6402 Datasheet(PDF) 55 Page - Intel Corporation

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