6402 datasheet(84/250 Pages) INTEL

84 / 250 page

Clocking

Intel® 6400/6402 Advanced Memory Buffer Datasheet

Figure 8-1. AMB Clock Domains

PLL

Reference Clock

Southbound

Data In

1x2

10x2

DRAM Clock

10x2

Southbound

Data Out

DRAM

Data / Strobe

72 + 18x2

Northbound

Data Out

Northbound

Data In

DRAM Clock #

DRAM Address /

Command Copy1

NORTH

SOUTH

SET

CLR

SET

CLR

SET

CLR

Data CRC Gen

& Read FIFO

deep

Write

Data

FIFO

Data Out

Cmd Out

Sync & Idle

Pattern

Generator

Command

Decoder &

CRC Check

External MEMBIST

DDR Calibration &

DDR IOBIST/DFX

Data In

SMbus

Controller

SMBus

Thermal

Sensor

mux

IBIST/DFX - RX

Link Init SM

and Control

JTAG

Controller

JTAG

14x2

mux

failover

14*6*2

IBIST/DFX -

Init Patterns

SB LAI Buffer

2 deep x 120

NB LAI Buffer

1 deep x 168

LAI data

SET

CLR

DRAM Address /

Command Copy2

DDR State

Controller

LAI

Controller

14x2

2x DDR + 2xbar

1x Rd DDR

4 phases of 6x

FBD

1x DDR/Core

failover

DRAM

Cmd

Core Control:

NB/SB Combined Init

Reset control

CSR chain control

Internal debug control

Reset

Init

patterns

SB Link

CSR’s

Data Merge

Re-synch

Re-Time

PISO

demux

10*12

State

and

control

Frame

clks and

state

Data Merge

Re-synch

Re-Time

PISO

demux

State

and

control

Frame

clks and

state

Link Init SM

and Control

NB Link

CSR’s

14*12

DDR

Link

CSR’s

10/17/03

Gold Bridge Block DIagram

1x fixed/

HVM

IBIST/DFX -

2x CA DDR

LAI Match and

Mask

IBIST/DFX -

Reset

Control

RefClk

Reset#

LAI data

AMB Block Diagram

6402 Datasheet(PDF) 84 Page - Intel Corporation

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