6402 datasheet(72/250 Pages) INTEL

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Errors

Intel® 6400/6402 Advanced Memory Buffer Datasheet

6.1.1.2

Errors during Channel Operation

Table 6-2.

Link Errors in Normal Operation (Sheet 1 of 2)

Error

Response

CRC Error on SB frame

“A” Command - detected by 14-bit CRC (or

reduced 10-bit CRC in Fail Over mode)

CRC Error on SB data or “BC” Commands

in Command Frame - detected by 22-bit

CRC (or reduced 10bit CRC in Fail Over

mode

If CMDCRC error type enabled in EMASK Register

No command executed

120-bit Raw SB Frame captured in RECFBD Error Log Registers

Type of error logged in FERR/NERR registers

Error/Alert Asserted bit set in FBD Status 0 register

Ignore future commands except Soft Channel Reset until Soft Channel Reset or

Link Reset Received

Alert Frame sent continuously starting with NB frame in which returned data

pattern would be sent if aborted command had been a config read. Alert

patterns continue until Soft Channel Reset or Link Fast Reset received.

Note:

Will NOT close DRAM pages or place DRAM into Self Refresh until detection

of Link Reset.

Else ignore error

Lose transition density on channel as

detected by no Sync in within 2 times the

SYNCTRAININT value (typically last 84

frames).

Note:

Purpose of this error is not to

detect violation of required

transition density (6 out of 512)

but to detect hang in the host and

put DRAM into self refresh. Any

corruption caused by lack of

transitions will be detected by

CRC violations.

If FEWEDGES error type enabled in EMASK Register

No command executed in expected Sync slot

120 bit Raw SB Frame captured in RECFBD Error Log Registers

Type of error logged in FERR/NERR registers

Error/Alert Asserted bit set in FBD Status 0 register

DDR Self Refresh FSM triggered to put DRAMs into Self Refresh

Ignore future commands including Soft Channel Reset until Link Reset

Received

Alert Frame sent continuously starting with NB frame in which returned data

pattern would be sent if aborted command had been a config read. Alert

patterns continue until Link Fast Reset received.

Else ignore error

Write Buffer Overrun

Write data received when FIFO is full

Overwriting the write buffer is a host error. The AMB does not take any action based

on an overrun. DRAM writes will proceed. What data item is written following an

overrun condition is not defined.

An overrun could be the result of channel errors, but these errors are detectable by

other means. Detection of an overrun condition is not required, but may be done by

implementation dependent means for debug.

Write Buffer Underrun:

not enough valid entries in Write FIFO to

support write data to memory

Underrunning the write buffer is a host error. The AMB does not take any action

based on an underrun. DRAM writes will proceed. What data item is written

following an underrun condition is not defined.

An underrun could be the result of channel errors, but these errors are detectable

by other means. Detection of an underrun condition is not required, but may be

done by implementation dependent means for debug.

6402 Datasheet(PDF) 72 Page - Intel Corporation

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