6402 datasheet(48/250 Pages) INTEL

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Electrical, Power, and Thermal

Intel® 6400/6402 Advanced Memory Buffer Datasheet

4.4.8

DQ and CB (ECC) Setup/Hold Relationships to/from DQS

(Read Operation)

Table 4-7 shows the timing diagram for tHDamb and tSUamb. The data is launched

from the DRAM “edge aligned,” meaning that the DQ data signals switch coincident with

the DQS strobe rising and falling edges. Internal to the Advance Memory Buffer, the

DQS strobe is delayed by approximately a quarter clock, and this delayed clock is then

used to capture the DQ data. Thus, the setup time tSUamb is negative, meaning that

the data can arrive at the Advance Memory Buffer inputs after the strobe, and tHDamb

is greater than a quarter clock, so that the data will not change until after it has been

captured by the internally delayed strobe. The Advance Memory Buffer determines the

correct internal delay of strobe DQS based on a search of the data eye during the

initialization of the system. The tHDamb and tSUamb specifications are based on an

idealized data eye, where the search delays the strobe by exactly one quarter clock.

The sum of tHDamb and tSUamb is equivalent to the minimum data valid window at

the Advance Memory Buffer inputs.

Figure 4-6. TDQSCK Timing Diagram

CLK (AMB)

DQS (AMB)

0.5xVCC

TDQSCK

Figure 4-7. DQ and CB (ECC) Setup/Hold Relationship to/from DQS Timing Diagram

observed at pins

DQS (AMB)

observed at pins

delayed internally

DQS (AMB)

delayed internally

DQ, CB (AMB)

observed at pins

tSUamb

tHDamb

DQS Delay

(90 deg. nom.)

tSUamb

DQS (AMB)

6402 Datasheet(PDF) 48 Page - Intel Corporation