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Intel® 6400/6402 Advanced Memory Buffer Datasheet

DDR Interface

3.5.1

Self-Refresh During Channel Reset

The Self-Refresh FSM is launched by a sync train error on the link, or when an electrical

idle condition is detected on the link. The Self-Refresh FSM will take the DRAM’s from

an unknown state and put them into self-refresh mode. The AMB does not track the

DRAM state during normal operation, and so has a single process for getting from any

DRAM state starting point to the self-refresh state.

When launched, the Self-Refresh FSM will execute the following steps. Each step below

is one of the states of the FSM. Setting the DRC.CKEFRCLOW bit will prevent the

command sequence described below from being issued on the DDR bus since it will

force the CKE outputs low.

1. Clear the DAREFTC.AREFEN CSR to stop the AMB auto-refresh engine if enabled.

2. Block all DRAM commands, except those initiated by the self-refresh FSM.

3. Wait until any in-process read or write commands complete, with a minimum wait

time of DSREFTC.TCKE, the DRAM “Minimum CKE pulse width time” specification.

In-process reads/writes must complete to ensure that the DRAM ODT control

outputs are driven low. The minimum time allows for the case where self-refresh

entry or power-down entry was executed just before the channel reset.

4. Assert both CKE output pins by setting the DRC.CKE0/1 CSR fields. This will have

no effect on the DRAM’s if the CKE pins were already asserted.

5. Wait DSREFTC.TXSNR, the DRAM’s “Exit self-refresh to a non-read command”

specification, to allow any in-process DRAM command to complete. This allows time

to complete any command that may have been issued just before the channel reset

event, such as an auto-refresh, as well as allows for self-refresh exit that may have

been initiated when the self-refresh FSM asserted the CKE pins high.

6. Issue a “precharge all” command to both ranks. This guarantees that the DRAM’s

will be in an “idle” state.

7. Wait as required by DSREFTC.TRP, the DRAM “Precharge time.”

8. Issue an auto-refresh command to both ranks. This meets the DRAM requirement

that at least one auto-refresh command is issued between any self-refresh exit to

self-refresh entry transition. The AMB staggers the auto-refresh commands to the

two ranks by the DSRETC.DRARTIM value in order to avoid stressing the system

power supply with too many DRAM’s refreshing at the same time.

9. Wait as required by DAREFTC.TRFC, the DRAM “Refresh to active/refresh command

time.”

10. Issue a self-refresh entry command to both ranks. The AMB staggers the self-

refresh entry commands to the two ranks by the DSRETC.DRSRENT value to avoid

stressing the system power supply.

When the channel comes out of “fast reset” (exiting the FBD link disable state), the

AMB will automatically issue a self-refresh exit command to both ranks after the FBD

Link Testing State is reached and the AMB core clock is stable. Note that this does not

apply when the DISSREXIT bit is set as it should be when the AMB is powering up or

when exiting S3 mode. The DRC.CKEFRCLOW CSR also overrides the automatic exit

command by forcing the CKE outputs to stay low.

3.5.2

Automatic Refresh

The AMB has an Auto-Refresh FSM for issuing auto-refresh commands to the DRAM’s

on regular intervals. This can be enabled when the DRAM bus is otherwise idle, but not

during any other mode that generates DRAM commands, including DRAM power up and

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