6402 datasheet(35/250 Pages) INTEL

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Intel® 6400/6402 Advanced Memory Buffer Datasheet

DDR Interface

3.9

DIMM Organization

The AMB supports DIMMs with 1 or 2 independent ranks (chip-selects). Each rank

consists of DDR SDRAM devices or DDR SDRAM devices. Dual rank DIMMs consist of

DDR SDRAM devices or DDR SDRAM devices.

The AMB DDR I/O circuits provide three main functions: an outbound command and

data path, an inbound data path, and analog compensation.

Analog compensation is provided, along with configuration registers, to control and

match the output impedance and slew rate of the off-chip drivers and on on-die

termination. The main configuration registers are the leg override (for impedance) and

slew override fields of the spdpar67cur and spdpar1011cur CSR’s. The analog

compensation circuits match driver characteristics to a ratio of an externally provided

resistance. The CSR’s control the ratio.

The outbound data path is relatively simple compared to the inbound. On the outbound

command, the I/O circuits provide a minimum latency, registered path to transfer

commands from the core to the DDR command bus as quickly as possible, but with

tight timing control. For the DQ, DQS, and DRAM clock outputs, the I/O provides

registered paths to transfer these signals to the DDR bus with the proper phase

relationship to the command. The phase of the DRAM clocks (along with the DQS and

DQ phase) relative to the command can be controlled by the ddr1xphsel and ca2xphsel

fields of the spdpar45cur and spdpar67cur CSR’s.

The inbound data path includes calibrated receiver enable circuits, calibrated DQS delay

lines, and an eight entry deep levelization FIFO. Calibration is controlled by the core at

power up and can take several ms to execute. Calibration involves a series of read and

write operations to the DRAM. Receiver enable is calibrated on a per byte basis. DQS

delay is calibrated at a coarse level on a word basis, with a fine calibration adjustment

for each nibble. The fine adjustment can be dynamic so that a different calibration

value can be sent from the core for each nibble depending on which rank is being

accessed. The core provides a read pointer to access the contents of the FIFO. The IO

I/O circuits manage the FIFO write pointer automatically, with timing based on both the

receiver enable and DQS delay calibrations.

6402 Datasheet(PDF) 35 Page - Intel Corporation