SC28L201 datasheet(53/110 Pages) NXP

53 / 110 page

9397 750 13138

Product data sheet

Rev. 01 — 31 October 2005

53 of 110

Philips Semiconductors

SC28L201

3.3 V, 5 V UART, 3.125 Mbit/s, with 256-byte FIFO

4:0

(cont.)

1 0000: Transmit an Xon character.

1 0001: Transmit an Xoff character.

1 0010: C/T start sets the counter timer to the value of the Counter/Timer

Preset Register and starts the counter.

1 0011: C/T stop. Effectively stops the counter/timer, captures the last

count value and resets the counter ready status bit in the ISR.

1 0100: reserved

1 0101: reserved

1 0110: Transmitter resume command (this command is not active in

‘Auto-Transmit mode’). A command to cancel a previous Host Xoff

command. Upon receipt, the channels transmitter will transfer a character,

if any, from the TxFIFO and begin transmission.

1 0111: Host Xoff (or transmitter pause) command (CRTXoff). This

command allows tight host CPU control of the ﬂow control of the channel

transmitter. When interrupted for receipt of an Xoff character by the

receiver, the host may stop transmission of further characters by the

channel transmitter by issuing the Host Xoff command. Any character that

has been transferred to the TXD shift register will complete its

transmission, including the stop bit before the transmitter pauses. Even

though the transmitter is paused it is still able to send Xon/Xoff by the

request of its associated receiver.

1 1000: Cancel Host transmit ﬂow control command. Issuing this

command will cancel a previous command to transmit a ﬂow control

character if the ﬂow control character is not yet loaded into the TXD Shift

transmission has already begun, then this command has no effect and the

character will be sent.

1 1001: reserved

1 1010: reserved

1 1011: Reset Address Recognition Status. This command clears the

interrupt status that was set when an address character was recognized by

a disabled receiver operating in the special mode.

1 1100: reserved

1 1101: Block error status accumulates on FIFO read (default state).

1 1110: reserved

1 1111: Executes a chip wide reset. Executing this command in Channel A

is equivalent to a hardware reset with the RESET(N) pin.

Table 23:

CRx - Command Register Extension (address 0x12) bit description …continued

Bit

Symbol

Description

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