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SC28L201 Datasheet(PDF) 98 Page - NXP Semiconductors

Part # SC28L201
Description  3.3 V, 5 V UART, 3.125 Mbit/s, with 256-byte FIFO
PDF  110 Pages
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Manufacturer  NXP [NXP Semiconductors]
Direct Link  http://www.nxp.com
Logo NXP - NXP Semiconductors

SC28L201 Datasheet(HTML) 98 Page - NXP Semiconductors

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9397 750 13138
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 01 — 31 October 2005
98 of 110
Philips Semiconductors
SC28L201
3.3 V, 5 V UART, 3.125 Mbit/s, with 256-byte FIFO
Fig 8.
Bus timing (80xxx mode)
DACKN LOW requires two rising edges of X1 clock after CEN is LOW.
Fig 9.
Bus timing, read cycle (68000 mode)
CEN
RDN
A0 to A6
tsu(An-RWL)
th(RWL-An)
tsu(RWL-CEN)
th(RWH-CEN)
tw(RWL)
td(RWD)
D0 to D7
(read)
float
valid
not valid
float
tDv(RL)
td(D)(float)
WRN
td(RWD)
D0 to D7
(write)
002aab475
valid
tsu(D)
th(D)
A0 to A6
tCSC
tsu(RWL-CEN)
tsu(An-RWL)
td(RWD)
D0 to D7
tDv(CENL)
td(D)(float)
002aab476
X1/SCLK
R/WN
CEN
th(RWH-CEN)
th(RWL-An)
not valid
data valid
DACKN
td(RL-D)(act)
tDCR
tDAT



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