SC28L201 datasheet(94/110 Pages) NXP

94 / 110 page

9397 750 13138

Product data sheet

Rev. 01 — 31 October 2005

94 of 110

Philips Semiconductors

SC28L201

3.3 V, 5 V UART, 3.125 Mbit/s, with 256-byte FIFO

Interrupt timing (see Figure 13)

td(int)

interrupt delay time

IRQN (or I/O[7:3]B when

used as interrupts) negated

from

read RxFIFO

(RxRDY/FFULL interrupt)

write TxFIFO

(TxRDY interrupt)

reset command (delta

break change interrupt)

stop C/T command

(Counter/Timer interrupt)

read IPCR (delta input

port change interrupt)

write IMR (clear of change

interrupt mask bit(s))

Clock timing (see Figure 14, Figure 15, and Figure 16)

tCLK

X1/SCLK HIGH or LOW time

fX1/SCLK

clock frequency on pin X1/SCLK 7.0 MHz to 16.2 MHz with

crystal

134150

MHz

tCTC

Counter/Timer clock HIGH or

LOW time

IP2; C/T external clock input

fCTC

Counter/Timer clock frequency

IP2

[5]

MHz

tRX

RxC HIGH or LOW time (16X)

fRX(16)

RxC frequency (16X)

MHz

fRX(1)

RxC frequency (1X)

[5] [6]

1.5

MHz

tTX

TxC HIGH or LOW time

fTX(16)

TxC frequency (16X)

MHz

fTX(1)

TxC frequency (1X)

[5] [6]

1.5

MHz

Transmitter timing (see Figure 15 and Figure 17)

td(o)(TXD)

TxC LOW to TXD output delay

time

TxC input pin

tTCS

TxC output pin LOW to

TXD data output delay time

Receiver timing (see Figure 16 and Figure 18)

tsu(RXD-RXCH)(D)

RXD to RxC HIGH data setup

time

20-20-

th(RXCH-RXD)(D)

RxC HIGH to RXD data hold

time

20-20-

68000 (Motorola) bus timing (see Figure 9, Figure 10, and Figure 11)

tsu(RWL-CEN)(mot) CEN LOW to RWN setup time

5-5-

tsu(D)(mot)

data bus to X1/SCLK HIGH

setup time

[7]

10-10-

Table 82:

Dynamic characteristics …continued

Tamb = −40 °C to +85 °C; voltage tolerance ± 10 %; unless otherwise speciﬁed. [1]

Symbol

Parameter

Conditions

VDD = 3.3 V

VDD =5V

Unit

Min

Max

Min

Max

SC28L201 Datasheet(PDF) 94 Page - NXP Semiconductors

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