SC28L201 datasheet(74/110 Pages) NXP

74 / 110 page

9397 750 13138

Product data sheet

Rev. 01 — 31 October 2005

74 of 110

Philips Semiconductors

SC28L201

3.3 V, 5 V UART, 3.125 Mbit/s, with 256-byte FIFO

8.6 Registers of the I/O ports

8.6.1 Input Port Change Register Lower Nibble, A (IPCRL)

This register may be read to determine the current logical level of the I/O pins and

examine the output of the change detectors assigned to each pin. If the change detection

is not enabled or if the pin is conﬁgured as an output, the associated change ﬁeld will read

‘0’.

Table 61:

IPCRL - Input Port Change Register Lower Nibble, A (address 0x14)

bit description

Bit

Symbol

Description

∆I/O3A change.

0 = no change

1 = change

∆I/O2A change.

0 = no change

1 = change

∆I/O1A change.

0 = no change

1 = change

∆I/O0A change.

0 = no change

1 = change

I/O3A state. Reads the actual logic level at the pin.

1 = HIGH level

0 = LOW level

I/O2A state. Reads the actual logic level at the pin.

1 = HIGH level

0 = LOW level

I/O1A state. Reads the actual logic level at the pin.

1 = HIGH level

0 = LOW level

I/O0A state. Reads the actual logic level at the pin.

1 = HIGH level

0 = LOW level

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