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WM8961GEFL/V Datasheet(PDF) 76 Page - Wolfson Microelectronics plc |
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WM8961GEFL/V Datasheet(HTML) 76 Page - Wolfson Microelectronics plc |
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76 / 116 page ![]() WM8961 Pre-Production w PP, August 2009, Rev 3.1 76 MASTER MODE BCLK CONFIGURATION The ADC and DAC must be configured to operate at the same sample rate. In master mode the BCLK and LRCLK_RATE must be configured to support this sample rate. The following Table 57 shows example calculations of the maximum word length supported for the ADC and DAC running at different sample rates. Note that ADCDIV, DACDIV and LRCLK_RATE must be configured to be the same sample rate. SYSCLK (MHz) SAMPLE RATE LRCLKRATE BCLKDIV BCLK RATE (MASTER MODE) (MHz) MAXIMUM WORD LENGTH (AT ADC/DAC SAMPLE RATE) 12.288 fs=48 kHz 0x100 =BCLK/256 = 48 kHz 0000 (=1) 12.288 (12.288 MHz/48 kHz) / 2 = 128. => 32 bit word length supported. 0x040 = BCLK/64 = 48 kHz 0100 (=4) 3.072 (3.072 MHz/48 kHz) / 2 = 32. => 32 bit word length supported. Fs=32 kHz 0x180 =BCLK/384 = 32 kHz 0000 (=1) 12.288 (12.288 MHz/32 kHz) / 2 = 192. => 32 bit word length supported. 0x040 = BCLK/64 = 32 kHz 0110 (=6) 2.048 (2.048 MHz/32 kHz) / 2 = 32. => 32 bit word length supported. 0x020 = BCLK/32 = 32 kHz 1001 (=12) 1.024 (1.024 MHz/32 kHz) / 2 = 16. => 16 bit word length supported. 11.2896 fs=44.1 kHz 0x100 =BCLK/256 = 44.1 kHz 0000 (=1) 11.2896 (11.2896MHz/44.1 kHz) / 2 = 128. => 32 bit word length supported. 0x040 = BCLK/64 = 44.1 kHz 0100 (=4) 2.8224 (2.8224MHz/44.1 kHz) / 2 = 32. => 32 bit word length supported. Fs=22.05 kHz 0x080 =BCLK/128 = 22.05 kHz 0100 (=4) 2.8224 (2.8224MHz/22.05 kHz) / 2 = 64. => 32 bit word length supported. Table 57 ADC and DAC Maximum Word Lengths Based on Valid BCLK (master mode) Configuration |
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