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WM8961GEFL/V Datasheet(PDF) 92 Page - Wolfson Microelectronics plc |
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WM8961GEFL/V Datasheet(HTML) 92 Page - Wolfson Microelectronics plc |
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92 / 116 page ![]() WM8961 Pre-Production w PP, August 2009, Rev 3.1 92 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R25 (19h) Pwr Mgmt (1) 8:7 VMIDSEL[1:0] 00 00 = off 01 = 2x50k 10 = 2x250k 11 = 2x5k 6 VREF 0 Enable master bias current source 5 AINL 0 Enables Left PGA and boost mixer 4 AINR 0 Enables Right PGA and boost mixer 3 ADCL 0 Enable ADC Left channel 2 ADCR 0 Enable ADC Right channel 1 MICB 0 Enable MICBIAS circuit Register 19h Pwr Mgmt (1) REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R26 (1Ah) Pwr Mgmt (2) 8 DACL 0 Enable left DAC channel 7 DACR 0 Enable right DAC channel 6 LOUT1_PGA 0 Enable left headphone PGA 5 ROUT1_PGA 0 Enable right headphone PGA 4 SPKL_PGA 0 Enable left speaker PGA 3 SPKR_PGA 0 Enable right speaker PGA Register 1Ah Pwr Mgmt (2) REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R27 (1Bh) Additional control (3) 2:0 SAMPLE_RATE[2:0] 000 Sample Rate Control for ALC and auto configuration 000 : 44.1k/48k 001 : 32k 010 : 22.05k/24k 011 : 16k 100 : 11.25k/12k 101 : 8k 110-111 : reserved Register 1Bh Additional control (3) REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R28 (1Ch) Anti-pop 4 BUFDCOPEN 0 Enables fast startup bias gen 3 BUFIOEN 0 Enables fast startup bias and vmid buffers 2 SOFT_ST 0 Enables VMID soft start 0 : Disabled 1 : Enabled Register 1Ch Anti-pop |
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