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WM8961GEFL/V Datasheet(PDF) 83 Page - Wolfson Microelectronics plc |
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WM8961GEFL/V Datasheet(HTML) 83 Page - Wolfson Microelectronics plc |
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83 / 116 page ![]() WM8961 Pre-Production w PP, August 2009, Rev 3.1 83 REGISTER BITS BY ADDRESS REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R0 (00h) Left Input volume 8 IPVU 0 Write 1 to do a volume update on inputs 7 LINMUTE 1 Left Input PGA Analogue Mute 1 = Enable Mute 0 = Disable Mute Note: IPVU must be set to un-mute. 6 LIZC 0 Zero cross enable. Requires separate register write before volume setting. 0 : Disable zero cross on left input PGA 1 : Enable zero cross 5:0 LINVOL[5:0] 01_1111 Left input PGA gain, 0.75dB steps 000000 : -23.25dB 000001 : -22.50dB … 011111 : 0dB … 111110 : 23.25dB 111111 : 24.00dB Register 00h Left Input volume REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R1 (01h) Right Input volume 15:12 DEVICE_ID [3:0] 0000 Reading from this register will indicate device family ID Device ID: [3:0] 0000 = 1801 0001-1111 : unused 11:9 CHIP_REV[2:0] 010 Device Revision: [2:0] 000 = Rev A 001 = Rev B 010 = Rev C 011-111 : unused 8 IPVU 0 Write 1 to do a volume update on inputs 7 RINMUTE 1 Right Input PGA Analogue Mute 1 = Enable Mute 0 = Disable Mute Note: IPVU must be set to un-mute. 6 RIZC 0 Zero cross enable. Requires separate register write before volume setting. 0 : Disable 1 : Enable 5:0 RINVOL[5:0] 01_1111 Right input PGA gain, 0.75dB steps 000000 : -23.25dB 000001 : -22.50dB … 011111 : 0dB … 111110 : 23.25dB 111111 : 24.00dB Register 01h Right Input volume |
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