OR3LP26B datasheet(138/184 Pages) AGERE

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ORCA OR3LP26B FPSC

Data Sheet

Embedded Master/Target PCI Interface

March 2000

138

Lucent Technologies Inc.

Timing Characteristics (continued)

Table 52. General-Purpose Clock Timing Characteristics (Internally Generated Clock)

OR3LP26B Commercial: VDD = 3.0 V to 3.6 V, 0 °C < TA < 70 °C; VDD2 = 2.38 V to 2.63 V, 0 °C < TA < 70 °C.

Notes:

This table represents the delay for an internally generated clock from the clock tree input in one of the four middle PICs (using pSW routing) on

any side of the device which is then distributed to the PFU/PIO clock inputs. If the clock tree input used is located at any other PIC, see the

results reported by

ORCA Foundry.

This clock delay is for a fully routed clock tree that uses the general clock network. The delay will be reduced if any of the clock branches are not

used. See pin-to-pin timing in Table 55 for clock delays of clocks input on general I/O pins.

Table 53. OR3LP26B ExpressCLK to Output Delay (Pin-to-Pin)

OR3LP26B Commercial: VDD = 3.0 V to 3.6 V, 0 °C < TA < 70 °C; VDD2 = 2.38 V to 2.63 V, 0 °C < TA < 70 °C.

Notes:

Timing is without the use of the programmable clock manager (PCM).

This clock delay is for a fully routed clock tree that uses the ExpressCLK network. It includes both the input buffer delay, the clock routing to the

PIO CLK input, the clock

→Q of the FF, and the delay through the output buffer. The given timing requires that the input clock pin be located at

one of the six ExpressCLK inputs of the device, and that a PIO FF be used.

5-4846(F).a

Figure 51. ExpressCLK to Output Delay

Device (TJ = 85 °C, VDD = min)

Symbol

Min

Max

Unit

OR3LP26B

clk_del

—

3.95

Description

(TJ = 85 °C, VDD = min)

Min

Max

Unit

ECLK Middle Input Pin

→OUTPUT Pin (Fast)

—5.82

ECLK Middle Input Pin

→OUTPUT Pin (Slewlim)

—6.61

ECLK Middle Input Pin

→OUTPUT Pin (Sinklim)

—

11.05

Additional Delay if ECLK Corner Pin Used

—

2.2

OUTPUT (50 pF LOAD)

ECLK

PIO FF

CLKCNTRL

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