OR3LP26B datasheet(135/184 Pages) AGERE

135 / 184 page

Lucent Technologies Inc.

135

Data Sheet

ORCA OR3LP26B FPSC

March 2000

Embedded Master/Target PCI Interface

Lucent Technologies Inc.

Electrical Characteristics

Table 48. Electrical Characteristics

OR3LP26B Commercial: VDD = 3.0 V to 3.6 V, VDD2 = 2.38 V to 2.63 V, 0 °C

< TA < 70 °C.

* On the Series 3 devices, the pull-up resistor will externally pull the pin to a level 1.0 V below VDD.

Parameter

Symbol

Test Conditions

OR3LP26B

Unit

Min

Max

Input Voltage:

High

Low

VIH

VIL

Input configured as CMOS

(clamped to VDD)

50% VDD

GND – 0.5

VDD + 0.3

30% VDD

Input Voltage:

High

Low

VIH

VIL

Input configured as TTL

(5 V tolerant)

50% VDD

GND – 0.5

5.8 V

30% VDD

Output Voltage:

High

Low

VOH

VOL

VDD = min, IOH = 6 mA or 3 mA

VDD = min, IOL = 12 mA or 6 mA

2.4

—

0.4

Input Leakage Current

VDD = max, VIN = VSS or VDD

–10

µA

Standby Current

IDDSB

(TA = 25 °C, VDD = 3.3 V, VDD2 = 2.5 V)

internal oscillator running, no output loads,

inputs at VDD or GND

(after configuration)

—TBD

Standby Current

IDDSB

(TA = 25 °C, VDD = 3.3 V, VDD2 = 2.5 V)

internal oscillator stopped, no output loads,

inputs at VDD or GND

(after configuration)

—TBD

Data Retention VoltageVDR

TA = 25 °C

TBD

—

Powerup Current

IPP

Power supply current at approximately

1 V, within a recommended power supply

ramp rate of 1 ms—200 ms

TBD

—

Input Capacitance

CIN

TA = 25 °C,

VDD = 3.3 V, VDD2 = 2.5 V

Test frequency = 1 MHz

—8

Output Capacitance

COUT

TA = 25 °C,

VDD = 3.3 V, VDD2 = 2.5 V

Test frequency = 1 MHz

—8

DONE Pull-up Resistor*

RDONE

—

100

—

Ω

M[3:0] Pull-up Resistors*

—

100

—

Ω

I/O Pad Static Pull-up

Current*

IPU

VDD = 3.6 V,

VIN = VSS, TA = 0 °C

14.4

50.9

µA

I/O Pad Static

Pull-down Current

IPD

VDD = 3.6 V,

VIN = VSS, TA = 0 °C

103

µA

I/O Pad Pull-up Resistor*

RPU

VDD = all, VIN = VSS, TA = 0 °C

100

—

Ω

I/O Pad Pull-down

Resistor

RPD

VDD = all, VIN = VDD, TA = 0 °C

—

Ω

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