OR3LP26B datasheet(133/184 Pages) AGERE

133 / 184 page

Lucent Technologies Inc.

133

Data Sheet

ORCA OR3LP26B FPSC

March 2000

Embedded Master/Target PCI Interface

Lucent Technologies Inc.

Powerup Sequencing for Series OR3LP26B Device

ORCA Series OR3LP26B device use two power supplies: one to power the device I/Os and the ASIC core (VDD)

which is set to 3.3 V for 3.3 V operation and 5 V tolerance, and another supply for the internal FPGA logic (VDD2)

which is set to 2.5 V. It is understood that many users will derive the 2.5 V core logic supply from a 3.3 V power

supply, so the following recommendations are made as to the powerup sequence of the supplies and allowable

delays between power supplies reaching stable voltages.

In general, both the 3.3 V and the 2.5 V supplies should ramp-up and become stable as close together in time as

possible. There is no delay requirement if the VDD2 (2.5 V) supply becomes stable prior to the VDD (3.3 V) supply.

There is a delay requirement imposed if the VDD supply becomes stable prior to the VDD2 supply.

The requirement is that the VDD2 (2.5 V) supply transition from 0 V to 2.3 V within 15.7 ms if the VDD (3.3 V) supply

is already stable at a minimum of 3.0 V. If the VDD supply has not yet reached 3.0 V when the VDD2 supply has

reached 2.3 V, then the requirement is that the VDD2 supply reach a minimum of 2.3 V within 15.7 ms of when the

VDD supply reaches 3.0 V.

If the chosen power supplies cannot meet this delay requirement, it is always possible to hold-off configuration of

the FPGA by asserting INIT or PRGM until the VDD2 supply has reached 2.3 V. This process eliminates any power

supply sequencing issues.

Absolute Maximum Ratings

Stresses in excess of the absolute maximum ratings can cause permanent damage to the device. These are abso-

lute stress ratings only. Functional operation of the device is not implied at these or any other conditions in excess

of those given in the operations sections of this data sheet. Exposure to absolute maximum ratings for extended

periods can adversely affect device reliability.

The

ORCA Series 3+ FPSCs include circuitry designed to protect the chips from damaging substrate injection cur-

rents and to prevent accumulations of static charge. Nevertheless, conventional precautions should be observed

during storage, handling, and use to avoid exposure to excessive electrical stress.

Table 46. Absolute Maximum Ratings

Note: For PCI bus signals used for 5 V signaling and FPGA inputs used as 5 V tolerant, the maximum value is 5.8 V.

Parameter

Symbol

Min

Max

Unit

Storage Temperature

Tstg

–65

150

°C

I/O and ASIC Supply Voltage with Respect to

Ground

VDD

—

≤4.2

Internal FPGA Supply Voltage with Respect

to Ground

VDD2—

≤3.2

Input Signal with Respect to Ground

CMOS Inputs

5 V Tolerant Inputs

—

–0.5

VDD + 0.3

5.8

Signal Applied to High-impedance Output

—

–0.5

VDD + 0.3

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