OR3LP26B datasheet(137/184 Pages) AGERE

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Lucent Technologies Inc.

137

Data Sheet

ORCA OR3LP26B FPSC

March 2000

Embedded Master/Target PCI Interface

Lucent Technologies Inc.

Timing Characteristics (continued)

In addition to supply voltage, process variation, and operating temperature, circuit and process improvements of

the

ORCA Series FPGAs over time will result in significant improvement of the actual performance over those

listed for a speed grade. Even though lower speed grades may still be available, the distribution of yield to timing

parameters may be several speed grades higher than that designated on a product brand. Design practices need

to consider best-case timing parameters (e.g., delays = 0), as well as worst-case timing.

The routing delays are a function of fan-out and the capacitance associated with the CIPs and metal interconnect

in the path. The number of logic elements that can be driven (fan-out) by PFUs is unlimited, although the delay to

reach a valid logic level can exceed timing requirements. It is difficult to make accurate routing delay estimates

prior to design compilation based on fan-out. This is because the CAE software may delete redundant logic

inserted by the designer to reduce fan-out, and/or it may also automatically reduce fan-out by net splitting.

The waveform test points are given in the Input/Output Buffer Measurement Conditions section of this data sheet.

The timing parameters given in the electrical characteristics tables in this data sheet follow industry practices, and

the values they reflect are described below.

Propagation Delay—The time between the specified reference points. The delays provided are the worst case of

the tphh and tpll delays for noninverting functions, tplh and tphl for inverting functions, and tphz and tplz for 3-state

enable.

Setup Time—The interval immediately preceding the transition of a clock or latch enable signal, during which the

data must be stable to ensure it is recognized as the intended value.

Hold Time—The interval immediately following the transition of a clock or latch enable signal, during which the

data must be held stable to ensure it is recognized as the intended value.

3-State Enable—The time from when a 3-state control signal becomes active and the output pad reaches the

high-impedance state.

Clock Timing

Table 51. ExpressCLK (ECLK) and Fast Clock (fclk) Timing Characteristics

OR3LP26B Commercial: VDD = 3.0 V to 3.6 V, 0 °C < TA < 70 °C; VDD2 = 2.38 V to 2.63 V, 0 °C < TA < 70 °C.

Notes:

The ECLK delays are to all of the PICs on one side of the device for middle pin input, or two sides of the device for corner pin input. The delay

includes both the input buffer delay and the clock routing to the PIC clock input.

The fclk delays are for a fully routed clock tree that uses the ExpressCLK input into the fast clock network. It includes both the input buffer delay

and the clock routing to the PFU CLK input. The delay will be reduced if any of the clock branches are not used.

Device

(TJ = 85 °C, VDD = min)

Symbol

Min

Max

Unit

ECLK Delay (middle pad)

eclkm_del

—

1.99

ECLK Delay (corner pad)

eclkc_del

—

4.20

fclk Delay (middle pad)

fclkm_del

—

5.24

fclk Delay (corner pad)

fclkc_del

—

7.46

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