OR3LP26B datasheet(140/184 Pages) AGERE

140 / 184 page

ORCA OR3LP26B FPSC

Data Sheet

Embedded Master/Target PCI Interface

March 2000

140

Lucent Technologies Inc.

Timing Characteristics (continued)

Table 55. OR3LP26B General System Clock (SCLK) to Output Delay (Pin-to-Pin)

OR3LP26B Commercial: VDD = 3.0 V to 3.6 V, 0 °C < TA < 70 °C; VDD2 = 2.38 V to 2.63 V, 0 °C < TA < 70 °C.

Note: This clock delay is for a fully routed clock tree that uses the primary clock network. It includes both the input buffer delay, the clock routing

to the PIO CLK input, the clock

→Q of the FF, and the delay through the output buffer. The delay will be reduced if any of the clock

branches are not used. The given timing requires that the input clock pin be located at one of the four center PICs on any side of the

device and that a PIO FF be used. For clock pins located at any other PIO, see the results reported by

ORCA Foundry.

5-4846(F)

Figure 53. System Clock to Output Delay

Description

(TJ = 85 °C, VDD = min)

Min

Max

Unit

Output On Same Side of Device As Input Clock (System Clock Delays Using General User I/O Inputs)

Clock Input Pin (mid-PIC)

→OUTPUT Pin (Fast)

—9.86

Clock Input Pin (mid-PIC)

→OUTPUT Pin (Slewlim)

—

10.66

Clock Input Pin (mid-PIC)

→OUTPUT Pin (Sinklim)

—

15.10

Additional Delay if Non-mid-PIC Used as Clock Pin

—

0.83

Output Not on Same Side of Device As Input Clock (System Clock Delays Using General User I/O Inputs)

Additional Delay if Output Not on Same Side as Input Clock Pin

—

0.83

OUTPUT (50 pF LOAD)

SCLK

PIO FF

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