ADSP-BF607 datasheet(61/112 Pages) AD

61 / 112 page

Rev. 0

Page 61 of 112

June 2013

ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609

Asynchronous Read

Table 28. Asynchronous Memory Read (BxMODE = b#00)

VDD_EXT

1.8 V/3.3V Nominal

Parameter

Min

Max

Unit

Timing Requirements

tSDATARE

DATA in Setup Before SMC0_ARE High

8.2

tHDATARE

DATA in Hold After SMC0_ARE High

tDARDYARE

SMC0_ARDY Valid After SMC0_ARE Low1, 2

(RAT – 2.5) × tSCLK0 – 17.5

Switching Characteristics

tADDRARE

SMC0_Ax/SMC0_AMSx Assertion Before SMC0_

ARE Low

(PREST + RST + PREAT) × tSCLK0 – 2

tAOEARE

SMC0_AOE Assertion Before SMC0_ARE Low

(RST + PREAT) × tSCLK0 – 2

tHARE

Output

4 Hold After SMC0_ARE High5

RHT × tSCLK0 –2

tWARE

SMC0_ARE Active Low Width

RAT × tSCLK0 – 2

tDAREARDY

SMC0_ARE High Delay After SMC0_ARDY

Assertion

2.5 × tSCLK0

3.5 × tSCLK0 + 17.5

1 SMC0_BxCTL.ARDYEN bit = 1.

2 RAT value set using the SMC_BxTIM.RAT bits.

3 PREST, RST, and PREAT values set using the SMC_BxETIM.PREST bits, SMC_BxTIM.RST bits, and the SMC_BxETIM.PREAT bits.

4 Output signals are SMC0_Ax, SMC0_AMS, SMC0_AOE, SMC0_ABEx.

5 RHT value set using the SMC_BxTIM.RHT bits.

6 SMC0_BxCTL.ARDYEN bit = 0.

Figure 12. Asynchronous Read

SMC0_ARE

SMC0_AMSx

SMC0_Ax

tWARE

SMC0_AOE

SMC0_Dx (DATA)

SMC0_ARDY

tAOEARE

tADDRARE

tDARDYARE

tHARE

tHDATARE

tDAREARDY

tSDATARE

ADSP-BF607 Datasheet(PDF) 61 Page - Analog Devices

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