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ADSP-BF607 Datasheet(PDF) 21 Page - Analog Devices |
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ADSP-BF607 Datasheet(HTML) 21 Page - Analog Devices |
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21 / 112 page ![]() Rev. 0 | Page 21 of 112 | June 2013 ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609 RSI_CLK Output Clock The clock signal applied to the connected device from the RSI. RSI_CMD I/O Command Used to send commands to and receive responses from the connected device. RSI_Dn I/O Data n Bidirectional data bus. SMC_ABEn Output Byte Enable n Indicate whether the lower or upper byte of a memory is being accessed. When an asynchronous write is made to the upper byte of a 16-bit memory, SMC_ABE1 =0 and SMC_ABE0 =1. When an asynchronous write is made to the lower byte of a 16-bit memory, SMC_ABE1 =1 and SMC_ABE0 =0. SMC_AMSn Output Memory Select n Typically connects to the chip select of a memory device. SMC_Ann Output Address n Address bus. SMC_AOE Output Output Enable Asserts at the beginning of the setup period of a read access. SMC_ARDY Input Asynchronous Ready Flow control signal used by memory devices to indicate to the SMC when further transactions may proceed. SMC_ARE Output Read Enable Asserts at the beginning of a read access. SMC_AWE Output Write Enable Asserts for the duration of a write access period. SMC_BG Output Bus Grant Output used to indicate to an external device that it has been granted control of the SMC buses. SMC_BGH Output Bus Grant Hang Output used to indicate that the SMC has a pending transaction which requires control of the bus to be restored before it can be completed. SMC_BR Input Bus Request Input used by an external device to indicate that it is requesting control of the SMC buses. SMC_Dnn I/O Data n Bidirectional data bus. SMC_NORCLK Output NOR Clock Clock for synchronous burst mode. SMC_NORDV Output NOR Data Valid Asserts for the duration of a synchronous burst mode read setup period. SMC_NORWT Input NOR Wait Flow control signal used by memory devices in synchronous burst mode to indicate to the SMC when further transactions may proceed. SPI_CLK I/O Clock Input in slave mode, output in master mode. SPI_D2 I/O Data 2 Used to transfer serial data in quad mode. Open drain in ODM mode. SPI_D3 I/O Data 3 Used to transfer serial data in quad mode. Open drain in ODM mode. SPI_MISO I/O Master In, Slave Out Used to transfer serial data. Operates in the same direction as SPI_MOSI in dual and quad modes. Open drain in ODM mode. SPI_MOSI I/O Master Out, Slave In Used to transfer serial data. Operates in the same direction as SPI_MISO in dual and quad modes. Open drain in ODM mode. SPI_RDY I/O Ready Optional flow signal. Output in slave mode, input in master mode. SPI_SELn Output Slave Select Output n Used in master mode to enable the desired slave. SPI_SS Input Slave Select Input Slave mode: acts as the slave select input. Master mode: optionally serves as an error detection input for the SPI when there are multiple masters. SPT_ACLK I/O Channel A Clock Data and frame sync are driven/sampled with respect to this clock. This signal can be either internally or externally generated. SPT_AD0 I/O Channel A Data 0 Primary bidirectional data I/O. This signal can be configured as an output to transmit serial data, or as an input to receive serial data. SPT_AD1 I/O Channel A Data 1 Secondary bidirectional data I/O. This signal can be configured as an output to transmit serial data, or as an input to receive serial data. SPT_AFS I/O Channel A Frame Sync The frame sync pulse initiates shifting of serial data. This signal is either generated internally or externally. SPT_ATDV Output Channel A Transmit Data Valid This signal is optional and only active when SPORT is configured in multi-channel transmit mode. It is asserted during enabled slots. SPT_BCLK I/O Channel B Clock Data and frame sync are driven/sampled with respect to this clock. This signal can be either internally or externally generated. SPT_BD0 I/O Channel B Data 0 Primary bidirectional data I/O. This signal can be configured as an output to transmit serial data, or as an input to receive serial data. Table 6. Detailed Signal Descriptions (Continued) Signal Name Direction Description |
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