ADSP-BF607 datasheet(71/112 Pages) AD

71 / 112 page

Rev. 0

Page 71 of 112

June 2013

ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609

Mobile DDR SDRAM Write Cycle Timing

Table 41. Mobile DDR SDRAM Write Cycle Timing, VDD_DMC Nominal 1.8 V

200 MHz

Parameter

Min

Max

Unit

Switching Characteristics

tDQSS

1 Write command to first DMC0_DQS delay = WL × t

CK + tDQSS.

DMC0_DQS Latching Rising Transitions to Associated Clock Edges

0.75

1.25

tCK

tDS

Last Data Valid to DMC0_DQS Delay (Slew > 1 V/ns)

0.48

tDH

DMC0_DQS to First Data Invalid Delay (Slew > 1 V/ns)

0.48

tDSS

DMC0_DQS Falling Edge to Clock Setup Time

0.2

tCK

tDSH

DMC0_DQS Falling Edge Hold Time From DMC0_CK

0.2

tCK

tDQSH

DMC0_DQS Input High Pulse Width

0.4

tCK

tDQSL

DMC0_DQS Input Low Pulse Width

0.4

tCK

tWPRE

Write Preamble

0.25

tCK

tWPST

Write Postamble

0.4

tCK

tIPW

Address and Control Output Pulse Width

2.3

tDIPW

DMC0_DQ and DMC0_DM Output Pulse Width

1.8

Figure 24. Mobile DDR SDRAM Controller Output AC Timing

DMC0_CK

DMC0_DQS0-1

DMC0_DQ0-15/

DMC0_DQM0-1

tDQSS

tDSH

tDSS

tDQSL

tDQSH

tWPST

tWPRE

tDS

tDH

tDIPW

CONTROL

Write CMD

Dn+1

Dn+2

Dn+3

NOTE: CONTROL =

DMC0_CS0, DMC0_CKE, DMC0_RAS, DMC0_CAS, AND DMC0_WE.

ADDRESS = DMC0_A00-13, AND DMC0_BA0-1.

tDIPW

tIPW

ADSP-BF607 Datasheet(PDF) 71 Page - Analog Devices

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