ADSP-BF607 datasheet(85/112 Pages) AD

85 / 112 page

Rev. 0

Page 85 of 112

June 2013

ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609

Serial Peripheral Interface (SPI) Port—Slave Timing

Table 52 and Figure 36 describe SPI port slave operations. Note

that:

• In dual mode data transmit the SPI_MOSI signal is also an

output.

• In quad mode data transmit the SPI_MOSI, SPI_D2, and

SPI_D3 signals are also outputs.

• In dual mode data receive the SPI_MISO signal is also an

input.

• In quad mode data receive the SPI_MISO, SPI_D2, and

SPI_D3 signals are also inputs.

Table 52. Serial Peripheral Interface (SPI) Port—Slave Timing

Parameter

VDD_EXT

1.8V/3.3V Nominal

Min

Max

Unit

Timing Requirements

tSPICHS

SPI_CLK High Period for Data Transmit

[0.5 × tSCLK1 – 1.5] or [7.0]

SPI_CLK High Period for Data Receive1

[0.5 × tSCLK1 – 1.5] or [4.5]

tSPICLS

SPI_CLK Low Period for Data Transmit

[0.5 × tSCLK1 – 1.5] or [7.0]

SPI_CLK Low Period for Data Receive1

[0.5 × tSCLK1 – 1.5] or [4.5]

tSPICLK

SPI_CLK Period for Data Transmit

[tSCLK1 – 1.5] or [17]

SPI_CLK Period for Data Receive1

[tSCLK1 – 1.5] or [12]

tHDS

Last SPI_CLK Edge to SPI_SS Not Asserted

tSPITDS

Sequential Transfer Delay

0.5 × tSPICLK – 1.5

tSDSCI

SPI_SS Assertion to First SPI_CLK Edge

10.5

tSSPID

Data Input Valid to SPI_CLK Edge (Data Input Setup)

2.0

tHSPID

SPI_CLK Sampling Edge to Data Input Invalid

1.6

Switching Characteristics

tDSOE

SPI_SS Assertion to Data Out Active

tDSDHI

SPI_SS Deassertion to Data High Impedance

12.5

tDDSPID

SPI_CLK Edge to Data Out Valid (Data Out Delay)

tHDSPID

SPI_CLK Edge to Data Out Invalid (Data Out Hold)

1 Whichever is greater.

ADSP-BF607 Datasheet(PDF) 85 Page - Analog Devices

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