ADSP-BF607 datasheet(13/112 Pages) AD

13 / 112 page

Rev. 0

Page 13 of 112

June 2013

ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609

A third counter input can provide flexible zero marker support

and can alternatively be used to input the push-button signal of

thumb wheels. All three pins have a programmable debouncing

circuit.

Internal signals forwarded to each general-purpose timer enable

these timers to measure the intervals between count events.

Boundary registers enable auto-zero operation or simple system

warning by interrupts when programmable count values are

exceeded.

Serial Peripheral Interface (SPI) Ports

The processors have two SPI-compatible ports that allow the

processor to communicate with multiple SPI-compatible

devices.

In its simplest mode, the SPI interface uses three pins for trans-

ferring data: two data pins (Master Output-Slave Input, MOSI,

and Master Input-Slave Output, MISO) and a clock pin (serial

clock, SPI_CLK). A SPI chip select input pin (SPI_SS) lets other

SPI devices select the processor, and seven SPI chip select out-

put pins (SPI_SEL7–1) let the processor select other SPI devices.

The SPI select pins are reconfigured general-purpose I/O pins.

Using these pins, the SPI port provides a full-duplex, synchro-

nous serial interface, which supports both master/slave modes

and multimaster environments.

In a multi-master or multi-slave SPI system, the MOSI and

MISO data output pins can be configured to behave as open

drain outputs (using the ODM bit) to prevent contention and

possible damage to pin drivers. An external pull-up resistor is

required on both the MOSI and MISO pins when this option is

selected.

When ODM is set and the SPI is configured as a master, the

MOSI pin is three-stated when the data driven out on MOSI is a

logic-high. The MOSI pin is not three-stated when the driven

data is a logic-low. Similarly, when ODM is set and the SPI is

configured as a slave, the MISO pin is three-stated if the data

driven out on MISO is a logic-high.

The SPI port’s baud rate and clock phase/polarities are pro-

grammable, and it has integrated DMA channels for both

transmit and receive data streams.

UART Ports

The processors provide two full-duplex universal asynchronous

receiver/transmitter (UART) ports, which are fully compatible

with PC-standard UARTs. Each UART port provides a simpli-

fied UART interface to other peripherals or hosts, supporting

full-duplex, DMA-supported, asynchronous transfers of serial

data. A UART port includes support for five to eight data bits,

and none, even, or odd parity. Optionally, an additional address

bit can be transferred to interrupt only addressed nodes in

multi-drop bus (MDB) systems. A frame is terminates by one,

one and a half, two or two and a half stop bits.

The UART ports support automatic hardware flow control

through the Clear To Send (CTS) input and Request To Send

(RTS) output with programmable assertion FIFO levels.

To help support the Local Interconnect Network (LIN) proto-

cols, a special command causes the transmitter to queue a break

command of programmable bit length into the transmit buffer.

Similarly, the number of stop bits can be extended by a pro-

grammable inter-frame space.

The capabilities of the UARTs are further extended with sup-

port for the Infrared Data Association (IrDA®) serial infrared

physical layer link specification (SIR) protocol.

TWI Controller Interface

The processors include a 2-wire interface (TWI) module for

providing a simple exchange method of control data between

multiple devices. The TWI module is compatible with the

widely used I2C bus standard. The TWI module offers the

capabilities of simultaneous master and slave operation and

support for both 7-bit addressing and multimedia data arbitra-

tion. The TWI interface utilizes two pins for transferring clock

(TWI_SCL) and data (TWI_SDA) and supports the protocol at

speeds up to 400k bits/sec. The TWI interface pins are compati-

ble with 5 V logic levels.

Additionally, the TWI module is fully compatible with serial

camera control bus (SCCB) functionality for easier control of

various CMOS camera sensor devices.

Removable Storage Interface (RSI)

The removable storage interface (RSI) controller acts as the host

interface for multimedia cards (MMC), secure digital memory

cards (SD), secure digital input/output cards (SDIO). The fol-

lowing list describes the main features of the RSI controller.

• Support for a single MMC, SD memory, SDIO card

• Support for 1-bit and 4-bit SD modes

• Support for 1-bit, 4-bit, and 8-bit MMC modes

• Support for eMMC 4.3 embedded NAND flash devices

• A ten-signal external interface with clock, command, and

up to eight data lines

• Card interface clock generation from SCLK0

• SDIO interrupt and read wait features

Controller Area Network (CAN)

A CAN controller implements the CAN 2.0B (active) protocol.

This protocol is an asynchronous communications protocol

used in both industrial and automotive control systems. The

CAN protocol is well suited for control applications due to its

capability to communicate reliably over a network. This is

because the protocol incorporates CRC checking, message error

tracking, and fault node confinement.

The CAN controller offers the following features:

• 32 mailboxes (8 receive only, 8 transmit only, 16 configu-

rable for receive or transmit).

• Dedicated acceptance masks for each mailbox.

• Additional data filtering on first two bytes.

• Support for both the standard (11-bit) and extended (29-

bit) identifier (ID) message formats.

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