ADSP-BF607 datasheet(22/112 Pages) AD

22 / 112 page

Rev. 0

Page 22 of 112

June 2013

ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609

SPT_BD1

I/O

Channel B Data 1 Secondary bidirectional data I/O. This signal can be configured as an output to

transmit serial data, or as an input to receive serial data.

SPT_BFS

I/O

Channel B Frame Sync The frame sync pulse initiates shifting of serial data. This signal is either

generated internally or externally.

SPT_BTDV

Output

Channel B Transmit Data Valid This signal is optional and only active when SPORT is configured in

multi-channel transmit mode. It is asserted during enabled slots.

SYS_BMODEn

Input

Boot Mode Control n Selects the boot mode of the processor.

SYS_CLKIN

Input

Clock/Crystal Input Connect to an external clock source or crystal.

SYS_CLKOUT

Output

Processor Clock Output Outputs internal clocks. Clocks may be divided down. See the CGU chapter in

the processor hardware reference for more details.

SYS_EXTWAKE

Output

External Wake Control Drives low during hibernate and high all other times. Typically connected to the

enable input of the voltage regulator controlling the VDD_INT supply.

SYS_FAULT

I/O

Complementary Fault Complement of SYS_FAULT.

SYS_FAULT

I/O

Fault Indicates internal faults or senses external faults depending on the operating mode.

SYS_HWRST

Input

Processor Hardware Reset Control Resets the device when asserted.

SYS_IDLEn

Output

Core n Idle Indicator When low indicates that core n is in idle mode or being held in reset.

SYS_NMI

Input

Non-maskable Interrupt Priority depends on the core that receives the interrupt. See the processor

hardware and programming references for more details.

SYS_PWRGD

Input

Power Good Indicator When high it indicates to the processor that the VDD_INT level is within specifica-

tions such that it is safe to begin booting upon return from hibernate.

SYS_RESOUT

Output

Reset Output Indicates that the device is in the reset state.

SYS_SLEEP

Output

Processor Sleep Indicator When low indicates that the processor is in the deep sleep power saving

mode.

SYS_TDA

Input

Thermal Diode Anode May be used by an external temperature sensor to measure the die temperature.

SYS_TDK

Input

Thermal Diode Cathode May be used by an external temperature sensor to measure the die

temperature.

SYS_XTAL

Output

Crystal Output Drives an external crystal. Must be left unconnected if an external clock is driving CLKIN.

TMR_ACIn

Input

Alternate Capture Input n Provides an additional input for WIDCAP, WATCHDOG, and PININT modes.

TMR_ACLKn

Input

Alternate Clock n Provides an additional time base for use by an individual timer.

TMR_CLK

Input

Clock Provides an additional global time base for use by all the GP timers.

TMR_TMRn

I/O

Timer n The main input/output signal for each timer.

TWI_SCL

I/O

Serial Clock Clock output when master, clock input when slave.

TWI_SDA

I/O

Serial Data Receives or transmits data.

UART_CTS

Input

Clear to Send Flow control signal.

UART_RTS

Output

Request to Send Flow control signal.

UART_RX

Input

Receive Receive input. Typically connects to a transceiver that meets the electrical requirements of the

device being communicated with.

UART_TX

Output

Transmit Transmit output. Typically connects to a transceiver that meets the electrical requirements of

the device being communicated with.

USB_CLKIN

Input

Clock/Crystal Input This clock input is multiplied by a PLL to form the USB clock. See Universal Serial

Bus (USB) On-The-Go—Receive and Transmit Timing for frequency/tolerance information.

USB_DM

I/O

Data – Bidirectional differential data line.

USB_DP

I/O

Data + Bidirectional differential data line.

USB_ID

Input

OTG ID Senses whether the controller is a host or device. This signal is pulled low when an A-type plug

is sensed (signifying that the USB controller is the A device), but the input is high when a B-type plug is

sensed (signifying that the USB controller is the B device).

USB_VBC

Output

VBUS Control Controls an external voltage source to supply VBUS when in host mode. May be

configured as open drain. Polarity is configurable as well.

USB_VBUS

I/O

Bus Voltage Connects to bus voltage in host and device modes.

Table 6. Detailed Signal Descriptions (Continued)

Signal Name

Direction

Description

ADSP-BF607 Datasheet(PDF) 22 Page - Analog Devices

ADSP-BF607 Datasheet(HTML) 22 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL