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ADSP-BF607 Datasheet(PDF) 95 Page - Analog Devices |
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ADSP-BF607 Datasheet(HTML) 95 Page - Analog Devices |
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95 / 112 page  Rev. 0 | Page 95 of 112 | June 2013 ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609 RSI Controller Timing Table 63 and Figure 49 describe RSI controller timing. Table 63. RSI Controller Timing VDD_EXT 1.8V Nominal VDD_EXT 3.3V Nominal Parameter Min Max Min Max Unit Timing Requirements tISU Input Setup Time 11 9.6 ns tIH Input Hold Time 2 2 ns Switching Characteristics fPP Clock Frequency Data Transfer Mode 1 41.67 41.67 MHz tWL Clock Low Time 8 8 ns tWH Clock High Time 8 8 ns tTLH Clock Rise Time 3 3 ns tTHL Clock Fall Time 3 3 ns tODLY Output Delay Time During Data Transfer Mode 2.5 2.5 ns tOH Output Hold Time –1 –1 ns 1 t PP = 1/fPP Figure 49. RSI Controller Timing RSI_CLK INPUT OUTPUT tISU NOTES: 1 INPUT INCLUDES RSI_Dx AND RSI_CMD SIGNALS. 2 OUTPUT INCLUDES RSI_Dx AND RSI_CMD SIGNALS. tTHL tTLH tWL tWH tPP tIH tODLY tOH VOH (MIN) VOL (MAX) |
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