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ADSP-BF607 Datasheet(PDF) 24 Page - Analog Devices |
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ADSP-BF607 Datasheet(HTML) 24 Page - Analog Devices |
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24 / 112 page  Rev. 0 | Page 24 of 112 | June 2013 ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609 DMC0_DQ00 DMC Data 0 Not Muxed DMC0_DQ00 DMC0_DQ01 DMC Data 1 Not Muxed DMC0_DQ01 DMC0_DQ02 DMC Data 2 Not Muxed DMC0_DQ02 DMC0_DQ03 DMC Data 3 Not Muxed DMC0_DQ03 DMC0_DQ04 DMC Data 4 Not Muxed DMC0_DQ04 DMC0_DQ05 DMC Data 5 Not Muxed DMC0_DQ05 DMC0_DQ06 DMC Data 6 Not Muxed DMC0_DQ06 DMC0_DQ07 DMC Data 7 Not Muxed DMC0_DQ07 DMC0_DQ08 DMC Data 8 Not Muxed DMC0_DQ08 DMC0_DQ09 DMC Data 9 Not Muxed DMC0_DQ09 DMC0_DQ10 DMC Data 10 Not Muxed DMC0_DQ10 DMC0_DQ11 DMC Data 11 Not Muxed DMC0_DQ11 DMC0_DQ12 DMC Data 12 Not Muxed DMC0_DQ12 DMC0_DQ13 DMC Data 13 Not Muxed DMC0_DQ13 DMC0_DQ14 DMC Data 14 Not Muxed DMC0_DQ14 DMC0_DQ15 DMC Data 15 Not Muxed DMC0_DQ15 DMC0_LDM DMC Data Mask for Lower Byte Not Muxed DMC0_LDM DMC0_LDQS DMC Data Strobe for Lower Byte Not Muxed DMC0_LDQS DMC0_LDQS DMC Data Strobe for Lower Byte (complement) Not Muxed DMC0_LDQS DMC0_ODT DMC On-die Termination Not Muxed DMC0_ODT DMC0_RAS DMC Row Address Strobe Not Muxed DMC0_RAS DMC0_UDM DMC Data Mask for Upper Byte Not Muxed DMC0_UDM DMC0_UDQS DMC Data Strobe for Upper Byte Not Muxed DMC0_UDQS DMC0_UDQS DMC Data Strobe for Upper Byte (complement) Not Muxed DMC0_UDQS DMC0_WE DMC Write Enable Not Muxed DMC0_WE ETH0_CRS EMAC0 Carrier Sense/RMII Receive Data Valid C PC_05 ETH0_MDC EMAC0 Management Channel Clock C PC_06 ETH0_MDIO EMAC0 Management Channel Serial Data C PC_07 ETH0_PTPPPS EMAC0 PTP Pulse-Per-Second Output B PB_15 ETH0_REFCLK EMAC0 Reference Clock B PB_14 ETH0_RXD0 EMAC0 Receive Data 0 C PC_00 ETH0_RXD1 EMAC0 Receive Data 1 C PC_01 ETH0_TXD0 EMAC0 Transmit Data 0 C PC_02 ETH0_TXD1 EMAC0 Transmit Data 1 C PC_03 ETH0_TXEN EMAC0 Transmit Enable B PB_13 ETH1_CRS EMAC1 Carrier Sense/RMII Receive Data Valid E PE_13 ETH1_MDC EMAC1 Management Channel Clock E PE_10 ETH1_MDIO EMAC1 Management Channel Serial Data E PE_11 ETH1_PTPPPS EMAC1 PTP Pulse-Per-Second Output C PC_09 ETH1_REFCLK EMAC1 Reference Clock G PG_06 ETH1_RXD0 EMAC1 Receive Data 0 G PG_00 ETH1_RXD1 EMAC1 Receive Data 1 E PE_15 ETH1_TXD0 EMAC1 Transmit Data 0 G PG_03 ETH1_TXD1 EMAC1 Transmit Data 1 G PG_02 ETH1_TXEN EMAC1 Transmit Enable G PG_05 ETH_PTPAUXIN EMAC0/EMAC1 PTP Auxiliary Trigger Input C PC_11 Table 7. ADSP-BF60x 349-Ball CSP_BGA Signal Descriptions (Continued) Signal Name Description Port Pin Name |
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