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ADSP-BF607 Datasheet(PDF) 23 Page - Analog Devices |
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ADSP-BF607 Datasheet(HTML) 23 Page - Analog Devices |
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23 / 112 page  Rev. 0 | Page 23 of 112 | June 2013 ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609 349-BALL CSP_BGA SIGNAL DESCRIPTIONS The processors' pin definitions are shown in the table. The col- umns in this table provide the following information: • Signal Name: The Signal Name column in the table includes the Signal Name for every pin. • Description: The Description column in the table provides a verbose (descriptive) name for the signal. • Port: The General-Purpose I/O Port column in the table shows whether or not the signal is multiplexed with other signals on a general-purpose I/O port pin. • Pin Name: The Pin Name column in the table identifies the name of the package pin (at power-on reset) on which the signal is located (if a single function pin) or is multiplexed (if a general-purpose I/O pin). Table 7. ADSP-BF60x 349-Ball CSP_BGA Signal Descriptions Signal Name Description Port Pin Name ACM0_A0 ACM0 Address 0 F PF_14 ACM0_A1 ACM0 Address 1 F PF_15 ACM0_A2 ACM0 Address 2 F PF_12 ACM0_A3 ACM0 Address 3 F PF_13 ACM0_A4 ACM0 Address 4 F PF_10 ACM0_CLK ACM0 Clock E PE_04 ACM0_FS ACM0 Frame Sync E PE_03 ACM0_T0 ACM0 External Trigger 0 E PE_08 ACM0_T1 ACM0 External Trigger 1 G PG_05 CAN0_RX CAN0 Receive G PG_04 CAN0_TX CAN0 Transmit G PG_01 CNT0_DG CNT0 Count Down and Gate G PG_12 CNT0_UD CNT0 Count Up and Direction G PG_11 CNT0_ZM CNT0 Count Zero Marker G PG_07 DMC0_A00 DMC Address 0 Not Muxed DMC0_A00 DMC0_A01 DMC Address 1 Not Muxed DMC0_A01 DMC0_A02 DMC Address 2 Not Muxed DMC0_A02 DMC0_A03 DMC Address 3 Not Muxed DMC0_A03 DMC0_A04 DMC Address 4 Not Muxed DMC0_A04 DMC0_A05 DMC Address 5 Not Muxed DMC0_A05 DMC0_A06 DMC Address 6 Not Muxed DMC0_A06 DMC0_A07 DMC Address 7 Not Muxed DMC0_A07 DMC0_A08 DMC Address 8 Not Muxed DMC0_A08 DMC0_A09 DMC Address 9 Not Muxed DMC0_A09 DMC0_A10 DMC Address 10 Not Muxed DMC0_A10 DMC0_A11 DMC Address 11 Not Muxed DMC0_A11 DMC0_A12 DMC Address 12 Not Muxed DMC0_A12 DMC0_A13 DMC Address 13 Not Muxed DMC0_A13 DMC0_BA0 DMC Bank Address Input 0 Not Muxed DMC0_BA0 DMC0_BA1 DMC Bank Address Input 1 Not Muxed DMC0_BA1 DMC0_BA2 DMC Bank Address Input 2 Not Muxed DMC0_BA2 DMC0_CAS DMC Column Address Strobe Not Muxed DMC0_CAS DMC0_CK DMC Clock Not Muxed DMC0_CK DMC0_CKE DMC Clock Enable Not Muxed DMC0_CKE DMC0_CK DMC Clock (complement) Not Muxed DMC0_CK DMC0_CS0 DMC Chip Select 0 Not Muxed DMC0_CS0 |
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