ADSP-BF607 datasheet(83/112 Pages) AD

83 / 112 page

Rev. 0

Page 83 of 112

June 2013

ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609

Serial Peripheral Interface (SPI) Port—Master Timing

Table 51 and Figure 35 describe SPI port master operations.

Note that:

• In dual mode data transmit the SPI_MISO signal is also an

output.

• In quad mode data transmit the SPI_MISO, SPI_D2, and

SPI_D3 signals are also outputs.

• In dual mode data receive the SPI_MOSI signal is also an

input.

• In quad mode data receive the SPI_MOSI, SPI_D2, and

SPI_D3 signals are also inputs.

Table 51. Serial Peripheral Interface (SPI) Port—Master Timing

Parameter

VDD_EXT

1.8V/3.3V Nominal

Min

Max

Unit

Timing Requirements

tSSPIDM

Data Input Valid to SPI_CLK Edge (Data Input Setup)

3.2

tHSPIDM

SPI_CLK Sampling Edge to Data Input Invalid

1.2

Switching Characteristics

tSDSCIM

SPI_SEL low to First SPI_CLK Edge1

[0.5 × tSCLK1 – 2] or [5]

tSPICHM

SPI_CLK High Period for Data Transmit

[0.5 × tSCLK1 – 1] or [5]

SPI_CLK High Period for Data Receive1

[0.5 × tSCLK1 – 1] or [5]

tSPICLM

SPI_CLK Low Period for Data Transmit

[0.5 × tSCLK1 – 1] or [5]

SPI_CLK Low Period for Data Receive1

[0.5 × tSCLK1 – 1] or [5]

tSPICLK

SPI_CLK Period for Data Transmit

[tSCLK1 – 1] or [12]

SPI_CLK Period for Data Receive1

[tSCLK1 – 1] or [13.33]

tHDSM

Last SPI_CLK Edge to SPI_SEL High

2 × tSCLK1 –1

tSPITDM

Sequential Transfer Delay

[0.5 × tSCLK1 – 1] or [5]

tDDSPIDM

SPI_CLK Edge to Data Out Valid (Data Out Delay)

2.6

tHDSPIDM

SPI_CLK Edge to Data Out Invalid (Data Out Hold)

–1

1 Whichever is greater.

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