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ADSP-BF607 Datasheet(PDF) 63 Page - Analog Devices

Part # ADSP-BF607
Description  Blackfin Dual Core Embedded Processor
PDF  112 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

ADSP-BF607 Datasheet(HTML) 63 Page - Analog Devices

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Rev. 0
|
Page 63 of 112
|
June 2013
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609
Asynchronous Page Mode Read
Table 30. Asynchronous Page Mode Read
VDD_EXT
1.8V /3.3V Nominal
Parameter
Min
Max
Unit
Switching Characteristics
tAV
SMC0_Ax (Address) Valid for First Address Min Width1
(PREST + RST + PREAT + RAT) × tSCLK0 – 2
ns
tAV1
SMC0_Ax (Address) Valid for Subsequent SMC0_Ax
(Address) Min Width
PGWS × tSCLK0 – 2
ns
tWADV
SMC0_NORDV Active Low Width
2
RST × tSCLK0 – 2
ns
tHARE
Output
3 Hold After SMC0_ARE High4
RHT × tSCLK0 – 2
ns
tWARE
5
SMC0_ARE Active Low Width
6
RAT × tSCLK0 – 2
ns
1 PREST, RST, PREAT and RAT values set using the SMC_BxETIM.PREST bits, SMC_BxTIM.RST bits, SMC_BxETIM.PREAT bits, and the SMC_BxTIM.RAT bits.
2 RST value set using the SMC_BxTIM.RST bits.
3 Output signals are SMC0_Ax, SMC0_AMSx, SMC0_AOE.
4 RHT value set using the SMC_BxTIM.RHT bits.
5 SMC_BxCTL.ARDYEN bit = 0.
6 RAT value set using the SMC_BxTIM.RAT bits.
Figure 14. Asynchronous Page Mode Read
SMC0_AMSx
(NOR_CE)
SMC0_ARE
(NOR_OE)
SMC0_AOE
NOR_ADV
SMC0_Dx
(DATA)
A0
tWADV
tWARE
tHARE
D0
D1
D2
D3
A0 + 1
A0 + 2
A0 + 3
tAV
tAV1
tAV1
tAV1
READ
LATCHED
DATA
READ
LATCHED
DATA
READ
LATCHED
DATA
READ
LATCHED
DATA
SMC0_Ax
(ADDRESS)



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