ADSP-BF607 datasheet(69/112 Pages) AD

69 / 112 page

Rev. 0

Page 69 of 112

June 2013

ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609

DDR2 SDRAM Write Cycle Timing

Table 38. DDR2 SDRAM Write Cycle Timing, VDD_DMC Nominal 1.8 V

250 MHz

1 In order to ensure proper operation of the DDR2, all the DDR2 guidelines have to be strictly followed.

Parameter

Min

Max

Unit

Switching Characteristics

tDQSS

2 Write command to first DMC0_DQS delay = WL × tCK + tDQSS.

DMC0_DQS Latching Rising Transitions to Associated Clock Edges

–0.15

0.15

tCK

tDS

Last Data Valid to DMC0_DQS Delay

0.15

tDH

DMC0_DQS to First Data Invalid Delay

0.3

tDSS

DMC0_DQS Falling Edge to Clock Setup Time

0.25

tCK

tDSH

DMC0_DQS Falling Edge Hold Time From DMC0_CK

0.25

tCK

tDQSH

DMC0_DQS Input High Pulse Width

0.35

tCK

tDQSL

DMC0_DQS Input Low Pulse Width

0.35

tCK

tWPRE

Write Preamble

0.35

tCK

tWPST

Write Postamble

0.4

tCK

tIPW

Address and Control Output Pulse Width

0.6

tCK

tDIPW

DMC0_DQ and DMC0_DM Output Pulse Width

0.35

tCK

Figure 21. DDR2 SDRAM Controller Output AC Timing

tDS

tDH

tDQSS

tDSH

tDSS

tWPRE

tDQSL

tDQSH

tWPST

DMC0_LDM

DMC0_CK

DMC0_A00

tIPW

tDIPW

DMC0_UDM

DMC0_LDQS

DMC0_UDQS

ADSP-BF607 Datasheet(PDF) 69 Page - Analog Devices

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