ADSP-BF607 datasheet(19/112 Pages) AD

19 / 112 page

Rev. 0

Page 19 of 112

June 2013

ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609

ADSP-BF60x DETAILED SIGNAL DESCRIPTIONS

Table 6 provides a detailed description of each signal.

Table 6. Detailed Signal Descriptions

Signal Name

Direction

Description

ACM_An

Output

ADC Control Signals Function varies by mode.

ACM_CLK

Output

Clock SCLK derived clock for connecting to an ADC.

ACM_FS

Output

Frame Sync Typically used as an ADC chip select.

ACM_Tn

Input

External Trigger n Input for external trigger events.

CAN_RX

Input

Receive Typically an external CAN transceiver's RX output.

CAN_TX

Output

Transmit Typically an external CAN transceiver's TX input.

CNT_DG

Input

Count Down and Gate Depending on the mode of operation this input acts either as a count down

signal or a gate signal.

Count Down: This input causes the GP counter to decrement.

Gate: Stops the GP counter from incrementing or decrementing.

CNT_UD

Input

Count Up and Direction Depending on the mode of operation this input acts either as a count up signal

or a direction signal.

Count Up: This input causes the GP counter to increment.

Direction: Selects whether the GP counter is incrementing or decrementing.

CNT_ZM

Input

Count Zero Marker Input that connects to the zero marker output of a rotary device or detects the

pressing of a push button.

DMC_Ann

Output

Address n Address bus.

DMC_BAn

Output

Bank Address Input n Defines which internal bank an ACTIVATE, READ, WRITE, or PRECHARGE command

is being applied to on the dynamic memory. Also defines which mode registers (MR, EMR, EMR2, and/or

EMR3) are loaded during the LOAD MODE REGISTER command.

DMC_CAS

Output

Column Address Strobe Defines the operation for external dynamic memory to perform in conjunction

with other DMC command signals. Connect to the CAS input of dynamic memory.

DMC_CK

Output

Clock (complement) Complement of DMC_CK.

DMC_CK

Output

Clock Outputs DCLK to external dynamic memory.

DMC_CKE

Output

Clock enable Active high clock enables. Connects to the dynamic memory’s CKE input.

DMC_CSn

Output

Chip Select n Commands are recognized by the memory only when this signal is asserted.

DMC_DQnn

I/O

Data n Bidirectional data bus.

DMC_LDM

Output

Data Mask for Lower Byte Mask for DMC_DQ07:DMC_DQ00 write data when driven high. Sampled on

both edges of the data strobe by the dynamic memory.

DMC_LDQS

I/O

Data Strobe for Lower Byte (complement) Complement of LDQS. Not used in single-ended mode.

DMC_LDQS

I/O

Data Strobe for Lower Byte DMC_DQ07:DMC_DQ00 data strobe. Output with Write Data. Input with

Read Data. May be single-ended or differential depending on register settings.

DMC_ODT

Output

On-die Termination Enables dynamic memory termination resistances when driven high (assuming

the memory is properly configured). ODT is enabled/disabled regardless of read or write commands.

DMC_RAS

Output

Row Address Strobe Defines the operation for external dynamic memory to perform in conjunction

with other DMC command signals. Connect to the RAS input of dynamic memory.

DMC_UDM

Output

Data Mask for Upper Byte Mask for DMC_DQ15:DMC_DQ08 write data when driven high. Sampled on

both edges of the data strobe by the dynamic memory.

DMC_UDQS

I/O

Data Strobe for Upper Byte (complement) Complement of UDQS. Not used in single-ended mode.

DMC_UDQS

I/O

Data Strobe for Upper Byte DMC_DQ15:DMC_DQ08 data strobe. Output with Write Data. Input with

Read Data. May be single-ended or differential depending on register settings.

DMC_WE

Output

Write Enable Defines the operation for external dynamic memory to perform in conjunction with other

DMC command signals. Connect to the WE input of dynamic memory.

ADSP-BF607 Datasheet(PDF) 19 Page - Analog Devices

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