TAS5760LDAPR datasheet(27/77 Pages) TI1

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TAS5760L

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SLOS782B – JULY 2013 – REVISED SEPTEMBER 2015

The minimum output offset voltages required to trigger the DC detect are listed in Table 2. The outputs must

remain at or above the voltage listed in the table for more than 420 msec to trigger the DC detect.

Table 2. DC Detect Threshold

PVDD [V]

|VOS|- OUTPUT OFFSET VOLTAGE [V]

4.5

0.96

1.30

2.60

9.4 Device Functional Modes

9.4.1 Hardware Control Mode

For systems which do not require the added flexibility of the I²C control port or do not have an I²C host controller,

the TAS5760L can be used in Hardware Control Mode. In this mode of operation, the device operates in its

default configuration and any changes to the device are accomplished via the hardware control pins, described

below. The audio performance between Hardware and Software Control mode is identical, however more

features and functionality are available when the device is operated in Software Control mode. The behavior of

these Hardware Control Mode pins is described in the sections below.

Several static I/O's are present on the TAS5760L which are meant to be configured during PCB design and not

changed during normal operation. Some examples of these are the GAIN[1:0] and PBTL/SCL pins. These pins

are often referred to as being tied or pulled LOW or tied or pulled HIGH. A pin which is tied or pulled LOW has

been connected directly to the system ground. The TAS5760L is configured such that the most popular use

cases for the device (that is BTL mode, 768-kHz switching frequency, and so forth) require the static I/O lines to

be tied LOW. This ensures optimum thermal performance as well as BOM reduction.

Device pins that need to be tied or pulled HIGH should be connected to DVDD. For these pins, a pull-up resistor

is recommended to limit the slew rate of the voltage which is presented to the pin during power up. Depending

on the output impedance of the supply, and the capacitance connected to the DVDD net on the board, slew rates

of this node could be high enough to trigger the integrated ESD protection circuitry at high current levels, causing

damage to the device. It is not necessary to have a separate pull-up resistor for each static digital I/O pin.

Instead, a single resistor can be connected to DVDD and all static I/O lines which are to be tied HIGH can be

connected to that pull-up resistor. This connectivity is shown in the Typical Application Circuits. These pullup

resistors are not required when the digital I/O pins are driven by a controlled driver, such as a digital control line

from a systems processor, as the output buffer in the system processor will ensure a controlled slew rate.

9.4.1.1 Speaker Amplifier Shut Down (SPK_SD Pin)

In both Hardware and Software Control mode, the SPK_SD pin is provided to place the speaker amplifier into

shutdown. Driving this pin LOW will place the device into shutdown, while pulling it HIGH (to DVDD) will bring the

device out of shutdown. This is the lowest power consumption mode that the device can be placed in while the

power supplies are up. If the device is placed into shutdown while in normal operation, an audible artifact may

occur on the output. To avoid this, the device should first be placed into sleep mode, by pulling the

SPK_SLEEP/ADR pin HIGH before pulling the SPK_SD low.

9.4.1.2 Serial Audio Port in Hardware Control Mode

When used in Hardware Control Mode, the Serial Audio Port (SAP) accepts only I²S formatted data. Additionally,

the device operates in Single-Speed Mode (SSM), which means that supported sample rates, MCLK rates, and

SCLK rates are limited to those shown in the table below. Additional clocking options, including higher sample

rates, are available when operating the device in Software Control Mode.

details the supported SCLK rates for each of the available sample rate and MCLK rate configurations. For each

fS and MCLK rate, the supported SCLK rates are shown and are represented in multiples of the sample rate,

which is written as "x fS".

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