TAS5760LDAPR datasheet(32/77 Pages) TI1

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TAS5760L

SLOS782B – JULY 2013 – REVISED SEPTEMBER 2015

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9.4.2.2.1

Serial Audio Port (SAP) Clocking

When used in Software Control mode, the device can be placed into double speed mode to support higher

sample rates, such as 88.2 kHz and 96 kHz. The tables below detail the supported SCLK rates for each of the

available sample rate and MCLK rate configurations. For each fS and MCLK Rate the support SCLK rates are

shown and are represented in multiples of the sample rate, which is written as "x fS".

Table 6. Supported SCLK Rates in Single-Speed Mode

MCLK Rate [x fS]

128

192

256

384

512

Sample Rate [kHz]

N/S

32, 48, 64

N/S

32, 48, 64

N/S

32, 48, 64

N/S

32, 48, 64

N/S

32, 48, 64

44.1

32, 48, 64

Table 7. Supported SCLK Rates in Double-Speed Mode

MCLK Rate [x fS]

128

192

256

Sample Rate [kHz]

88.2

32, 48, 64

9.4.2.3 Parallel Bridge Tied Load Mode via Software Control

The TAS5760L can be configured to drive a single speaker with the two output channels connected in parallel.

This mode of operation is called Parallel Bridge Tied Load (PBTL) mode. This mode of operation effectively

reduces the on resistance of the amplifier in half, which in turn reduces the power dissipated in the device due to

conduction losses through the output FETs. Additionally, since the output channels are working in parallel, it also

doubles the amount of current the speaker amplifier can source before hitting the over-current error threshold.

It should be noted that the device can be placed operated in PBTL mode in either Hardware Control Mode or in

Software Control Mode, via the I²C Control Port. For instructions on placing the device in PBTL via the

PBTL/SCL Pin, see Hardware Control Mode.

To place the TAS5760L into PBTL Mode when operating in Software Control Mode, the Bit 7 of the Analog

Control Register (0x06) should be set in the control port. This bit is cleared by default to configure the device for

BTL mode operation. An additional control available in software mode control is PBTL Channel Select, which

selects which of the two channels presented on the SDIN line will be used for the input signal for the amplifier.

This is found at Bit 1 of the Analog Control Register (0x06). When operated in PBTL mode, the output pins

should be connected as shown in the Typical Application Circuit Diagrams.

9.4.2.4 Speaker Amplifier Gain Structure

As shown in Figure 43, the audio path of the TAS5760L consists of a digital audio input port, a digital audio path,

a digital to analog converter, an analog modulator, a gate driver stage, a Class D power stage, and a feedback

loop which feeds the output information back into the analog modulator to correct for distortion sensed on the

output pins. The total amplifier gain is comprised of digital gain, shown as GDIG in the digital audio path and the

analog gain from the input of the analog modulator GANA to the output of the speaker amplifier power stage.

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