 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
TAS5760LDAPR Datasheet(PDF) 6 Page - Texas Instruments |
|
|
|
|||||||||||||||||||||||||||||
TAS5760LDAPR Datasheet(HTML) 6 Page - Texas Instruments |
|
|
6 / 77 page  ANA_REG SFT_CLIP AVDD VCOM ANA_REF SPK_FAULT FREQ/SDA SPK_SD PBTL/SCL DVDD GVDD_REG GGND BSTRPA+ SPK_OUTA+ PVDD PGND SPK_OUTA- BSTRPA- BSTRPB- SPK_OUTB- SPK_GAIN0 SPK_GAIN1 SPK_SLEEP/ADR SCLK PGND PVDD SPK_OUTB+ DGND BSTRPB+ LRCK MCLK SDIN PowerPAD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 TAS5760L SLOS782B – JULY 2013 – REVISED SEPTEMBER 2015 www.ti.com DAP PACKAGE 32-PIN TSSOP TOP VIEW Pin Functions TAS5760L INTERNAL NO. TYPE(1) DESCRIPTION TERMINATION NAME AVDD 1 P - Power supply for internal analog circuitry Connection point for internal reference used by ANA_REG and VCOM filter ANA_REF 5 P - capacitors Voltage regulator derived from AVDD supply (NOTE: This terminal is provided ANA_REG 3 P - as a connection point for filtering capacitors for this supply and must not be used to power any external circuitry) Connection point for the SPK_OUTA- bootstrap capacitor, which is used to BSTRPA- 25 P - create a power supply for the high-side gate drive for SPK_OUTA- Connection point for the SPK_OUTA+ bootstrap capacitor, which is used to BSTRPA+ 30 P - create a power supply for the high-side gate drive for SPK_OUTA Connection point for the SPK_OUTB- bootstrap capacitor, which is used to BSTRPB- 24 P - create a power supply for the high-side gate drive for SPK_OUTB- Connection point for the SPK_OUTB+ bootstrap capacitor, which is used to BSTRPB+ 19 P - create a power supply for the high-side gate drive for SPK_OUTB+ Ground for digital circuitry (NOTE: This terminal should be connected to the DGND 18 G - system ground) DVDD 10 P - Power supply for the internal digital circuitry Dual function terminal that functions as an I²C data input terminal in I²C Control FREQ/SDA 8 DI Weak Pull-Down Mode or as a Frequency Select terminal when in Hardware Control Mode. Ground for gate drive circuitry (this terminal should be connected to the system GGND 31 G - ground) Voltage regulator derived from PVDD supply (NOTE: This terminal is provided GVDD_REG 32 P - as a connection point for filtering capacitors for this supply and must not be used to power any external circuitry) Word select clock for the digital signal that is active on the serial port's input LRCK 17 DI Weak Pull-Down data line Master Clock used for internal clock tree, sub-circuit/state machine, and Serial MCLK 14 DI Weak Pull-Down Audio Port clocking Dual function terminal that functions as an I²C clock input terminal in I²C PBTL/SCL 9 DI Weak Pull-Down Control Mode or configures the device to operate in pre-filter Parallel Bridge Tied Load (PBTL) mode when in Hardware Control Mode (1) AI = Analog input, AO = Analog output, DI = Digital Input, DO = Digital Output, P = Power, G = Ground (0V) 6 Submit Documentation Feedback Copyright © 2013–2015, Texas Instruments Incorporated Product Folder Links: TAS5760L |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
