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TAS5760LDAPR Datasheet(PDF) 8 Page - Texas Instruments |
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TAS5760LDAPR Datasheet(HTML) 8 Page - Texas Instruments |
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8 / 77 page  TAS5760L SLOS782B – JULY 2013 – REVISED SEPTEMBER 2015 www.ti.com 7.3 Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT TA Ambient Operating Temperature –25 85 °C AVDD AVDD Supply 4.5 16.5 V PVDD PVDD Supply 4.5 16.5 V DVDD DVDD Supply 2.8 3.63 V VIH(DR) Input Logic HIGH for DVDD Referenced Digital Inputs DVDD V VIL(DR) Input Logic LOW for DVDD Referenced Digital Inputs 0 V RSPK (BTL) Minimum Speaker Load in BTL Mode 4 Ω RSPK (PBTL) Minimum Speaker Load in PBTL Mode 2 Ω 7.4 Thermal Information TAS5760L DCA DCA DAP DAP THERMAL METRIC(1) UNIT [HTSSOP] [HTSSOP] [HTSSOP] [HTSSOP] 32-PIN(2) 48-PIN(2) 32-PIN(3) 48-PIN(3) θJA Junction-to-ambient thermal resistance 60.3 30.2 60.3 31.9 °C/W θJC(top) Junction-to-case (top) thermal resistance 16 14.3 16 16 °C/W θJB Junction-to-board thermal resistance 12 12.7 12 17 °C/W ψJT Junction-to-top characterization parameter 0.4 0.6 0.4 0.4 °C/W ψJB Junction-to-board characterization parameter 11.9 12.7 11.9 16.8 °C/W θJC(bott Junction-to-case (bottom) thermal resistance 0.8 0.7 0.8 0.81 °C/W om) (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953. (2) JEDEC Standard 2 Layer Board (3) JEDEC Standard 4 Layer Board 7.5 Digital I/O Pins over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Input Logic HIGH threshold for DVDD VIH1 All digital pins 70 %DVDD Referenced Digital Inputs Input Logic LOW threshold for DVDD VIL1 All digital pins 30 %DVDD Referenced Digital Inputs IIH1 Input Logic HIGH Current Level All digital pins 15 µA IIL1 Input Logic LOW Current Level All digital pins –15 µA VOH Output Logic HIGH Voltage Level IOH = 2 mA 90 %DVDD VOL Output Logic LOW Voltage Level IOH = -2 mA 10 %DVDD 7.6 Master Clock over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT DMCLK Allowable MCLK Duty Cycle 45% 50% 55% MCLK Input Frequency 25 MHz Supported single-speed MCLK Values: 64, 128, 192, 256, 384, 64 512 fMCLK Frequencies and 512 x fs Supported double-speed MCLK Values: 64, 128, and 256 64 256 Frequencies 8 Submit Documentation Feedback Copyright © 2013–2015, Texas Instruments Incorporated Product Folder Links: TAS5760L |
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