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TAS5760LDAPR Datasheet(PDF) 63 Page - Texas Instruments |
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TAS5760LDAPR Datasheet(HTML) 63 Page - Texas Instruments |
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63 / 77 page  10 F 0.22uF 10k Top Layer Ground and PowerPad Top Layer Signal Traces Via to bottom Ground Plane Top Layer Ground Pour System Processor Via to PVDD TAS5760L 26 25 28 27 30 32 31 29 23 24 22 19 20 17 18 0.22uF 10 F 10 F 15 16 13 14 11 12 9 10 7 8 5 6 1 3 4 2 10 F 0.22uF 0.22uF 21 TAS5760L www.ti.com SLOS782B – JULY 2013 – REVISED SEPTEMBER 2015 Layout Example (continued) Figure 56. DAP Package BTL Configuration Copyright © 2013–2015, Texas Instruments Incorporated Submit Documentation Feedback 63 Product Folder Links: TAS5760L |
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