TAS5760LDAPR datasheet(35/77 Pages) TI1

35 / 77 page

A0 R/W ACK A7

A0 ACK

ACK

Start

Condition

Stop

Condition

Acknowledge

I CDevice Addressand

Read/WriteBit

Subaddress

DataByte

D0 ACK

I CDevice Addressand

Read/WriteBit

Not

Acknowledge

R/W

RepeatStart

Condition

T0036-03

R/W ACK A7

ACK

D0 ACK

Start

Condition

Stop

Condition

Acknowledge

I CDevice Addressand

Read/WriteBit

Subaddress

DataByte

T0036-01

TAS5760L

www.ti.com

SLOS782B – JULY 2013 – REVISED SEPTEMBER 2015

9.4.2.5.3

Writing to the I²C Control Port

As shown in Figure 45, a single-byte data-write transfer begins with the master device transmitting a START

condition followed by the I²C and the read/write bit. The read/write bit determines the direction of the data

transfer. For a data-write transfer, the read/write bit is a 0. After receiving the correct I²C and the read/write bit,

the TAS5760L responds with an acknowledge bit. Next, the master transmits the address byte corresponding to

the TAS5760L register being accessed. After receiving the address byte, the TAS5760L again responds with an

acknowledge bit. Next, the master device transmits the data byte to be written to the memory address being

accessed. After receiving the data byte, the TAS5760L again responds with an acknowledge bit. Finally, the

master device transmits a STOP condition to complete the single-byte data-write transfer.

Figure 45. Write Transfer

9.4.2.5.4

Reading from the I²C Control Port

As shown in Figure 46, a data-read transfer begins with the master device transmitting a START condition,

followed by the I²C device address and the read/write bit. For the data read transfer, both a write followed by a

read are actually done. Initially, a write is done to transfer the address byte of the internal register to be read. As

a result, the read/write bit becomes a 0. After receiving the TAS5760L address and the read/write bit, TAS5760L

responds with an acknowledge bit. In addition, after sending the internal memory address byte or bytes, the

master device transmits another START condition followed by the TAS5760L address and the read/write bit

again. This time, the read/write bit becomes a 1, indicating a read transfer. After receiving the address and the

read/write bit, the TAS5760L again responds with an acknowledge bit. Next, the TAS5760L transmits the data

byte from the register being read. After receiving the data byte, the master device transmits a not-acknowledge

followed by a STOP condition to complete the data-read transfer.

Figure 46. Read Transfer

9.5 Register Maps

9.5.1 Control Port Registers - Quick Reference

Table 8. Control Port Quick Reference Table

Default (Binary)

Adr.

Default

(Dec)

(Hex)

Device Identification

Device

0x00

Identification

SPK_SL

DigClipLev[19:14]

SPK_SD

EEP

Power Control

0xFD

Submit Documentation Feedback

Product Folder Links: TAS5760L

TAS5760LDAPR Datasheet(PDF) 35 Page - Texas Instruments

TAS5760LDAPR Datasheet(HTML) 35 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77

Datasheet Download

Link URL