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TMS320C6745DPTP3 Datasheet(PDF) 116 Page - Texas Instruments |
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TMS320C6745DPTP3 Datasheet(HTML) 116 Page - Texas Instruments |
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116 / 227 page  RMII_MHz_50_CLK RMII_TXEN RMII_TXD[1:0] RMII_RXD[1:0] RMII_CRS_DV RMII_RXER 1 2 3 5 5 4 6 7 8 9 10 11 TMS320C6745, TMS320C6747 SPRS377F – SEPTEMBER 2008 – REVISED JUNE 2014 www.ti.com Table 6-37. EMAC Control Module RAM BYTE ADRESS REGISTER DESCRIPTION 0x01E2 0000 - 0x01E2 1FFF EMAC Local Buffer Descriptor Memory Table 6-38. RMII Timing Requirements No. PARAMETER MIN TYP MAX UNIT 1 tc(REFCLK) Cycle Time, RMII_MHZ_50_CLK 20 ns 2 tw(REFCLKH) Pulse Width, RMII_MHZ_50_CLK High 7 13 ns 3 tw(REFCLKL) Pulse Width, RMII_MHZ_50_CLK Low 7 13 ns 6 tsu(RXD-REFCLK) Input Setup Time, RXD Valid before RMII_MHZ_50_CLK High 4 ns 7 th(REFCLK-RXD) Input Hold Time, RXD Valid after RMII_MHZ_50_CLK High 2 ns 8 tsu(CRSDV-REFCLK) Input Setup Time, CRSDV Valid before RMII_MHZ_50_CLK High 4 ns 9 th(REFCLK-CRSDV) Input Hold Time, CRSDV Valid after RMII_MHZ_50_CLK High 2 ns 10 tsu(RXER-REFCLK) Input Setup Time, RXER Valid before RMII_MHZ_50_CLK High 4 ns 11 th(REFCLKR-RXER) Input Hold Time, RXER Valid after RMII_MHZ_50_CLK High 2 ns Note: Per the RMII industry specification, the RMII reference clock (RMII_MHZ_50_CLK) must have jitter tolerance of 50 ppm or less. Table 6-39. RMII Switching Characteristics No. PARAMETER MIN TYP MAX UNIT 4 td(REFCLK-TXD) Output Delay Time, RMII_MHZ_50_CLK High to TXD Valid 2.5 13 ns 5 td(REFCLK-TXEN) Output Delay Time, RMII_MHZ_50_CLK High to TXEN Valid 2.5 13 ns Figure 6-30. RMII Timing Diagram 116 Peripheral Information and Electrical Specifications Copyright © 2008–2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS320C6745 TMS320C6747 |
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