TMS320C6745DPTP3 datasheet(123/227 Pages) TI1

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TMS320C6745, TMS320C6747

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SPRS377F – SEPTEMBER 2008 – REVISED JUNE 2014

Table 6-45. McASP Registers Accessed Through DMA Port

Hex

McASP0

McASP1

McASP2

Address

Name

BYTE

ADDRESS

Read

RBUF

01D0 2000

01D0 6000

01D0 A000

Receive buffer DMA port address. Cycles through receive serializers,

Accesses

skipping over transmit serializers and inactive serializers. Starts at the

lowest serializer at the beginning of each time slot. Reads from DMA port

only if RBUSEL = 0 in RFMT.

Write

XBUF

01D0 2000

01D0 6000

01D0 A000

Transmit buffer DMA port address. Cycles through transmit serializers,

Accesses

skipping over receive and inactive serializers. Starts at the lowest

serializer at the beginning of each time slot. Writes to DMA port only if

XBUSEL = 0 in XFMT.

Table 6-46. McASP AFIFO Registers Accessed Through Peripheral Configuration Port

McASP0

McASP1

McASP2

ACRONYM

BYTE ADDRESS

0x01D0 1000

0x01D0 5000

0x01D0 9000

AFIFOREV

AFIFO revision identification register

0x01D0 1010

0x01D0 5010

0x01D0 9010

WFIFOCTL

Write FIFO control register

0x01D0 1014

0x01D0 5014

0x01D0 9014

WFIFOSTS

Write FIFO status register

0x01D0 1018

0x01D0 5018

0x01D0 9018

RFIFOCTL

Read FIFO control register

0x01D0 101C

0x01D0 501C

0x01D0 901C

RFIFOSTS

Read FIFO status register

Peripheral Information and Electrical Specifications

123

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