TMS320C6745DPTP3 datasheet(124/227 Pages) TI1

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TMS320C6745, TMS320C6747

SPRS377F – SEPTEMBER 2008 – REVISED JUNE 2014

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6.16.2 McASP Electrical Data/Timing

6.16.2.1 Multichannel Audio Serial Port 0 (McASP0) Timing

Table 6-47 and Table 6-48 assume testing over recommended operating conditions (see Figure 6-34 and

Figure 6-35).

Table 6-47. McASP0 Timing Requirements(1) (2)

No.

PARAMATER

MIN

MAX

UNIT

Cycle time, AHCLKR0 external, AHCLKR0 input

tc(AHCLKRX)

Cycle time, AHCLKX0 external, AHCLKX0 input

Pulse duration, AHCLKR0 external, AHCLKR0 input

12.5

tw(AHCLKRX)

Pulse duration, AHCLKX0 external, AHCLKX0 input

12.5

Cycle time, ACLKR0 external, ACLKR0 input

greater of 2P or 25

tc(ACLKRX)

Cycle time, ACLKX0 external, ACLKX0 input

greater of 2P or 25

Pulse duration, ACLKR0 external, ACLKR0 input

12.5

tw(ACLKRX)

Pulse duration, ACLKX0 external, ACLKX0 input

12.5

Setup time, AFSR0 input to ACLKR0 internal(3)

9.4

Setup time, AFSX0 input to ACLKX0 internal

9.4

Setup time, AFSR0 input to ACLKR0 external input (3)

2.9

tsu(AFSRX-ACLKRX)

Setup time, AFSX0 input to ACLKX0 external input

2.9

Setup time, AFSR0 input to ACLKR0 external output (3)

2.9

Setup time, AFSX0 input to ACLKX0 external output

2.9

Hold time, AFSR0 input after ACLKR0 internal(3)

-1.2

Hold time, AFSX0 input after ACLKX0 internal

-1.2

Hold time, AFSR0 input after ACLKR0 external input (3)

0.9

th(ACLKRX-AFSRX)

Hold time, AFSX0 input after ACLKX0 external input

0.9

Hold time, AFSR0 input after ACLKR0 external output (3)

0.9

Hold time, AFSX0 input after ACLKX0 external output

0.9

Setup time, AXR0[n] input to ACLKR0 internal (3)

9.4

Setup time, AXR0[n] input to ACLKX0 internal(4)

9.4

Setup time, AXR0[n] input to ACLKR0 external input (3)

2.9

tsu(AXR-ACLKRX)

Setup time, AXR0[n] input to ACLKX0 external input (4)

2.9

Setup time, AXR0[n] input to ACLKR0 external output (3)

2.9

Setup time, AXR0[n] input to ACLKX0 external output (4)

2.9

Hold time, AXR0[n] input after ACLKR0 internal(3)

-1.3

Hold time, AXR0[n] input after ACLKX0 internal (4)

-1.3

Hold time, AXR0[n] input after ACLKR0 external input (3)

0.5

th(ACLKRX-AXR)

Hold time, AXR0[n] input after ACLKX0 external input (4)

0.5

Hold time, AXR0[n] input after ACLKR0 external output (3)

0.5

Hold time, AXR0[n] input after ACLKX0 external output (4)

0.5

(1)

ACLKX0 internal – McASP0 ACLKXCTL.CLKXM = 1, PDIR.ACLKX = 1

ACLKX0 external input – McASP0 ACLKXCTL.CLKXM = 0, PDIR.ACLKX = 0

ACLKX0 external output – McASP0 ACLKXCTL.CLKXM = 0, PDIR.ACLKX = 1

ACLKR0 internal – McASP0 ACLKRCTL.CLKRM = 1, PDIR.ACLKR =1

ACLKR0 external input – McASP0 ACLKRCTL.CLKRM = 0, PDIR.ACLKR = 0

ACLKR0 external output – McASP0 ACLKRCTL.CLKRM = 0, PDIR.ACLKR = 1

(2)

P = SYSCLK2 period

(3)

McASP0 ACLKXCTL.ASYNC=1: Receiver is clocked by its own ACLKR0

(4)

McASP0 ACLKXCTL.ASYNC=0: Receiver is clocked by transmitter's ACLKX0

124

Peripheral Information and Electrical Specifications

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