TNETV1647GSTZWT datasheet(180/236 Pages) TI1

180 / 236 page

PCLK

(Positive Edge Clocking)

PCLK

(Negative Edge Clocking)

VCTL(A)

A. VCTL = HSYNC and VSYNC

VPBECLK

LCD_FIELD

TMS320DM6441

SPRS359E – SEPTEMBER 2006 – REVISED AUGUST 2010

www.ti.com

Table 6-61. Timing Requirements for VPBE Control Input With Respect to PCLK and VPBECLK(1)

(see Figure 6-51)

1.05 V and 1.2 V

NO.

UNIT

MIN

MAX

tsu(VCTLV-VCLKIN)

Setup time, VCTL valid before VCLKIN edge

th(VCLKIN-VCTLV)

Hold time, VCTL valid after VCLKIN edge

0.5

tsu(VCTLV-VPBECLK) Setup time, VCTL valid before VPBECLK rising edge

th(VPBECLK-VCTLV)

Hold time, VCTL valid after VPBECLK rising edge

0.5

tsu(FIELD-PCLK)

Setup time, LCD_FIELD valid before PCLK edge

5P(2)

th(PCLK-FIELD)

Hold time, LCD_FIELD valid after PCLK edge

5P(2)

tsu(FIELD-VPBECLK)

Setup time, LCD_FIELD valid before VPBECLK edge

5P(2)

th(VPBECLK-FIELD)

Hold time, LCD_FIELD valid after VPBECLK edge

5P(2)

(1)

PCLK may be configured to operate in either positive or negative edge clocking mode. When in positive edge clocking mode, the rising

edge of PCLK is referenced. When in negative edge clocking mode, the falling edge of PCLK is referenced.

(2)

P = 1/(VCLKIN clock frequency) in ns. VCLKIN is either PCLK or VPBECLK, whichever is used.

Figure 6-51. VPBE Input Timing With Respect to PCLK and VPBECLK

180

Peripheral and Electrical Specifications

Submit Documentation Feedback

Product Folder Link(s): TMS320DM6441

TNETV1647GSTZWT Datasheet(PDF) 180 Page - Texas Instruments

TNETV1647GSTZWT Datasheet(HTML) 180 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL