TNETV1647GSTZWT datasheet(63/236 Pages) TI1

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TMS320DM6441

www.ti.com

SPRS359E – SEPTEMBER 2006 – REVISED AUGUST 2010

Device Configurations

3.1

System Module Registers

The system module includes status and control registers required for configuration of the device. Brief

descriptions of the various registers are shown in Table 3-1. System module registers required for device

configurations are discussed in the following sections.

Table 3-1. System Module Register Memory Map

HEX ADDRESS RANGE

DESCRIPTION

0x01C4 0000

PINMUX0

Pin multiplexing control 0. See Section 3.5.4, PINMUX0 Register Description,

for details.

0x01C4 0004

PINMUX1

Pin multiplexing control 1. See Section 3.5.5, PINMUX1 Register Description,

for details.

0x01C4 0008

DSPBOOTADDR

Boot address of DSP. See Section 3.3.1.2, DSPBOOTADDR Register

Description, for details.

0x01C4 000C

SUSPSRC

Emulator Suspend Source. See Section 3.6, Emulation Control, for details.

0x01C4 0010

INTGEN

ARM/DSP Interrupt Status and Control. See Section 6.7.3, ARM/DSP

Communications Interrupts, for details.

0x01C4 0014

BOOTCFG

Device boot configuration. See Section 3.3.1.1, BOOTCFG Register

Description, for details.

0x01C4 0018 - 0x01C4 0027

–

Reserved

0x01C4 0028

JTAGID

JTAGID/Device ID number. See Section 6.26.1, JTAG Peripheral Register

Description(s) – JTAG ID Register, for details.

0x01C4 002C

–

Reserved

0x01C4 0030

HPI_CTL

HPI control. See Section 3.5.6.10, HPI and EMIFA/ATA Pin Multiplexing, for

details.

0x01C4 0034

USBPHY_CTL

USB PHY control. See Section 6.14.1, USBPHY_CTL Register Description,

for details.

0x01C4 0038

CHP_SHRTSW

Chip shorting switch control. See Section 3.2.1, Power Configurations at

Reset, for details.

0x01C4 003C

MSTPRI0

Bus master priority control 0. See Section 3.5.1, Switched Central Resource

(SCR) Bus Priorities, for details.

0x01C4 0040

MSTPRI1

Bus master priority control 1. See Section 3.5.1, Switched Central Resource

(SCR) Bus Priorities, for details.

0x01C4 0044

VPSS_CLKCTL

VPSS clock control.

0x01C4 0048

VDD3P3V_PWDN

VDD 3.3V I/O powerdown control. See Section 3.2.2, Power Configurations

after Reset, for details.

0x01C4 004C

DRRVTPER

Enables access to the DDR2 VTP register.

0x01C4 0050 - 0x01C4 006F –

Reserved

3.2

Power Considerations

Global device power domains are controlled by the power and sleep controller, except as shown in the

following sections.

Device Configurations

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